PIC17C44-08SLASHP datasheet(21/240 Pages) MICROCHIP

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DS30412C-page 21

PIC17C4X

5.0

INTERRUPTS

The PIC17C4X devices have 11 sources of interrupt:

• External interrupt from the RA0/INT pin

• Change on RB7:RB0 pins

• TMR0 Overﬂow

• TMR1 Overﬂow

• TMR2 Overﬂow

• TMR3 Overﬂow

• USART Transmit buffer empty

• USART Receive buffer full

• Capture1

• Capture2

• T0CKI edge occurred

There are four registers used in the control and status

of interrupts. These are:

• CPUSTA

• INTSTA

• PIE

• PIR

The CPUSTA register contains the GLINTD bit. This is

the Global Interrupt Disable bit. When this bit is set, all

interrupts are disabled. This bit is part of the controller

core functionality and is described in the Memory Orga-

nization section.

When an interrupt is responded to, the GLINTD bit is

automatically set to disable any further interrupt, the

return address is pushed onto the stack and the PC is

loaded with the interrupt vector address. There are four

interrupt vectors. Each vector address is for a speciﬁc

interrupt source (except the peripheral interrupts which

have the same vector address). These sources are:

• External interrupt from the RA0/INT pin

• TMR0 Overﬂow

• T0CKI edge occurred

• Any peripheral interrupt

When program execution vectors to one of these inter-

rupt vector addresses (except for the peripheral inter-

rupt address), the interrupt ﬂag bit is automatically

cleared. Vectoring to the peripheral interrupt vector

address does not automatically clear the source of the

interrupt. In the peripheral interrupt service routine, the

source(s) of the interrupt can be determined by testing

the interrupt ﬂag bits. The interrupt ﬂag bit(s) must be

cleared in software before re-enabling interrupts to

avoid inﬁnite interrupt requests.

All of the individual interrupt ﬂag bits will be set regard-

less of the status of their corresponding mask bit or the

GLINTD bit.

For external interrupt events, there will be an interrupt

latency. For two cycle instructions, the latency could be

one instruction cycle longer.

The “return from interrupt” instruction, RETFIE, can be

used to mark the end of the interrupt service routine.

When this instruction is executed, the stack is

“POPed”, and the GLINTD bit is cleared (to re-enable

interrupts).

FIGURE 5-1:

INTERRUPT LOGIC

TMR1IF

TMR1IE

TMR2IF

TMR2IE

TMR3IF

TMR3IE

CA1IF

CA1IE

CA2IF

CA2IE

TXIF

TXIE

RCIF

RCIE

RBIF

RBIE

T0IF

T0IE

INTF

INTE

T0CKIF

T0CKIE

GLINTD

PEIE

Wake-up (If in SLEEP mode)

or terminate long write

Interrupt to CPU

PEIF

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