PIC16LC710-10SLASHP datasheet(44/176 Pages) MICROCHIP

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PIC16C71X

DS30272A-page 44

7.5

A/D Operation During Sleep

The A/D module can operate during SLEEP mode. This

requires that the A/D clock source be set to RC

(ADCS1:ADCS0 = 11). When the RC clock source is

selected, the A/D module waits one instruction cycle

before starting the conversion. This allows the SLEEP

instruction to be executed, which eliminates all digital

switching noise from the conversion. When the conver-

sion is completed the GO/DONE bit will be cleared, and

the result loaded into the ADRES register. If the A/D

interrupt is enabled, the device will wake-up from

SLEEP. If the A/D interrupt is not enabled, the A/D mod-

ule will then be turned off, although the ADON bit will

remain set.

When the A/D clock source is another clock option (not

RC), a SLEEP instruction will cause the present conver-

sion to be aborted and the A/D module to be turned off,

though the ADON bit will remain set.

Turning off the A/D places the A/D module in its lowest

current consumption state.

7.6

A/D Accuracy/Error

The absolute accuracy speciﬁed for the A/D converter

includes the sum of all contributions for quantization

error, integral error, differential error, full scale error, off-

set error, and monotonicity. It is deﬁned as the maxi-

mum deviation from an actual transition versus an ideal

transition for any code. The absolute error of the A/D

converter is speciﬁed at <

±1 LSb for VDD = VREF (over

the device’s speciﬁed operating range). However, the

accuracy of the A/D converter will degrade as VDD

diverges from VREF.

For a given range of analog inputs, the output digital

code will be the same. This is due to the quantization of

the analog input to a digital code. Quantization error is

typically

± 1/2 LSb and is inherent in the analog to dig-

ital conversion process. The only way to reduce quanti-

zation error is to increase the resolution of the A/D

converter.

Offset error measures the ﬁrst actual transition of a

code versus the ﬁrst ideal transition of a code. Offset

error shifts the entire transfer function. Offset error can

be calibrated out of a system or introduced into a sys-

tem through the interaction of the total leakage current

and source impedance at the analog input.

Gain error measures the maximum deviation of the last

actual transition and the last ideal transition adjusted

for offset error. This error appears as a change in slope

of the transfer function. The difference in gain error to

Note:

For the A/D module to operate in SLEEP,

the A/D clock source must be set to RC

(ADCS1:ADCS0 = 11). To perform an A/D

conversion in SLEEP, ensure the SLEEP

instruction immediately follows the instruc-

tion that sets the GO/DONE bit.

full scale error is that full scale does not take offset error

into account. Gain error can be calibrated out in soft-

ware.

Linearity error refers to the uniformity of the code

changes. Linearity errors cannot be calibrated out of

the system. Integral non-linearity error measures the

actual code transition versus the ideal code transition

adjusted by the gain error for each code.

Differential non-linearity measures the maximum

actual code width versus the ideal code width. This

measure is unadjusted.

In systems where the device frequency is low, use of

the A/D RC clock is preferred. At moderate to high fre-

quencies, TAD should be derived from the device oscil-

lator. TAD must not violate the minimum and should be

≤ 8 µs for preferred operation. This is because TAD,

when derived from TOSC, is kept away from on-chip

phase clock transitions. This reduces, to a large extent,

the effects of digital switching noise. This is not possible

with the RC derived clock. The loss of accuracy due to

digital switching noise can be signiﬁcant if many I/O

pins are active.

In systems where the device will enter SLEEP mode

after the start of the A/D conversion, the RC clock

source selection is required. In this mode, the digital

noise from the modules in SLEEP are stopped. This

method gives high accuracy.

7.7

Effects of a RESET

A device reset forces all registers to their reset state.

This forces the A/D module to be turned off, and any

conversion is aborted.

The value that is in the ADRES register is not modiﬁed

for a Power-on Reset. The ADRES register will contain

unknown data after a Power-on Reset.

7.8

Connection Considerations

If the input voltage exceeds the rail values (VSS or VDD)

by greater than 0.2V, then the accuracy of the conver-

sion is out of speciﬁcation.

An external RC ﬁlter is sometimes added for anti-alias-

ing of the input signal. The R component should be

selected to ensure that the total source impedance is

kept under the 10 k

Ω recommended speciﬁcation. Any

external components connected (via hi-impedance) to

an analog input pin (capacitor, zener diode, etc.) should

have very little leakage current at the pin.

Note:

Care must be taken when using the RA0

pin in A/D conversions due to its proximity

to the OSC1 pin.

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