LM3524DM datasheet(20/29 Pages) TI

20 / 29 page

LM2524D, LM3524D

SNVS766E – JUNE 2009 – REVISED MAY 2013

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So far it is assumed

η = 100%, where the actual efficiency or ηMAX will be somewhat less due to the saturation

voltage of Q1 and forward on voltage of D1. The internal power loss due to these voltages is the average IL

current flowing, or IIN, through either VSAT or VD1. For VSAT = VD1 = 1V this power loss becomes IIN(DC) (1V). ηMAX

is then:

(21)

(22)

This equation assumes only DC losses, however

ηMAX is further decreased because of the switching time of Q1

and D1.

In calculating the output capacitor Co it can be seen that Co supplies Io during tON. The voltage change on Co

during this time will be some

ΔVc = ΔVo or the output ripple of the regulator. Calculation of Co is:

(23)

where: Co is in farads, f is the switching frequency,

ΔVo is the p-p output ripple

Calculation of inductor L1 is as follows:

(24)

VIN is applied across L1

(25)

where: L1 is in henrys, f is the switching frequency in Hz

To apply the above theory, a complete step-up switching regulator is shown in Figure 30. Since VIN is 5V, VREF is

tied to VIN. The input voltage is divided by 2 to bias the error amplifier's inverting input. The output voltage is:

(26)

The network D1, C1 forms a slow start circuit.

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