数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

ML2037 数据表(PDF) 4 Page - Micro Linear Corporation

部件名 ML2037
功能描述  500kHz, Serial Input, Programmable Sine Wave Generator with Digital Gain Control
PDF  10 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  MICRO-LINEAR [Micro Linear Corporation]
网页  http://www.microlinear.com
标志 MICRO-LINEAR - Micro Linear Corporation

ML2037 数据表(HTML) 4 Page - Micro Linear Corporation

  ML2037 Datasheet HTML 1Page - Micro Linear Corporation ML2037 Datasheet HTML 2Page - Micro Linear Corporation ML2037 Datasheet HTML 3Page - Micro Linear Corporation ML2037 Datasheet HTML 4Page - Micro Linear Corporation ML2037 Datasheet HTML 5Page - Micro Linear Corporation ML2037 Datasheet HTML 6Page - Micro Linear Corporation ML2037 Datasheet HTML 7Page - Micro Linear Corporation ML2037 Datasheet HTML 8Page - Micro Linear Corporation ML2037 Datasheet HTML 9Page - Micro Linear Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 10 page
background image
ML2037
4
Note 1:
Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
OSCILLATOR (Continued)
tR
CLK OUT Rise Time
CL = 25pF, See Timing Diagram 2
8
ns
tF
CLK OUT Fall Time
CL = 25pF, See Timing Diagram 2
8
ns
LOGIC
VIL
Input Low Voltage
1.0
V
VIH
Input High Voltage
DVCC - 1
V
IIL
Input Low Current
-1
µA
IIH
Input High Current
1µA
VOL
Output Low Voltage
IOL = -2mA
0.4
V
VOH
Output High Voltage
IOH = 2mA
4.0
V
fS CLK
Serial Clock Frequency
0.01
10
MHz
tPW
Serial CLock Pulse Width
40
ns
tSSD
S DATA IN Setup Time
10
ns
tHSD
S DATA IN Hold Time
10
ns
tSSENS
S ENABLE Setup Time
30
ns
tSSENH
S ENABLE Hold Time
50
ns
tDSEN
Delay from S ENABLE to Stable Output
fCLK IN = 32MHz
500
ns
tDSYNC
Delay from SYNC to Output Start
fCLK IN = 32MHz
500
ns
SUPPLY
AICC
AVCC Current
fCLK IN = 16MHz
35
45
mA
fCLK IN = 32MHz
40
50
mA
SHDN = 5V
10
µA
DICC
DVCC Current
fCLK IN = 16MHz
10
14
mA
fCLK IN = 32MHz
16
20
mA
SHDN = 5V
30
µA
fCLK OUT
fCLK IN
tR
tF
CLK IN
CLK OUT
Timing Diagram 1.
Timing Diagram 2.
tSSENS
tSSENH
S CLK
S DATA IN
S ENABLE
tSSD
tHSD
tPW
tPW
D0
D1
D2
D14
D15



Html Pages

1 2 3 4 5 6 7 8 9 10


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com