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ML2652/ML2653

The controller interface consists of seven pins. TxC, TxD,

and TxE are the transmit clock output, transmit data input,

and transmit data enable input, respectively. RxC, RxD,

and RxE are the receive clock output, receive data output,

and receive data enable output, respectively. COL is the

collision detect output.

All the standard Ethernet controllers use a similar

controller interface but differ in the polarity of COL, LPBK,

TxE and RxE, and in what edge of TxC and RxC that clocks

in the data. They also differ on whether the RxC clock

needs to be continuous or not during idle, and on the

polarity of RxD during idle. In order to accommodate the

different controller interface definitions, the controller

select pins, CS2–0, modify these signals according to

Table 1.

POWERDOWN

The device can be placed in the power down mode with

the controller select pins CS2–0 as described in Table 1.

When in powerdown mode, the current consumption is

reduced to less than ZmA and all device functions are

disabled.

CRYSTAL OSCILLATOR

The ML2652 requires an accurate 20 MHz reference for

internal clock generation. This can be achieved by

connecting an external crystal or an external clock

between the CLK and GND pins.

If an external clock is used, it must have a frequency of

20 MHz ±0.01% and have high and low levels of 3.5 and

1.5 volts.

If a crystal is used, the crystal should be placed physically

as close as possible to the CLK and GND pins, especially

CLK. No other external capacitors or components are

required. The crystal should have the following

characteristics:

1. Parallel resonant type

2. Frequency: 20 MHz

3. Tolerance: ±0.005% @ 25°C

4. Less than 0.005% frequency drift across

temperature.

5. Maximum equiv. series resistance:

15 ohms @ 1–200µW

30 ohms @ 0.01–1µW

6. Typical load capacitance: 20pF

7. Maximum case capacitance: 5pF

Table 1. Controller Select Pin Definitions

Idl

Idl

CS2–0

TxC

TxE

RxC

RxE

COL

LPBK

RxC

RxD

Controller

0 0 0

r

h

r

h

h

h

m

l

NSC

DP8390

0 0 1

flfl

l

l

n

hi

Intel

82586/96

0 1 0

r

h

r

h

h

h

n

hi

AMD

AM7990

Motorola*

0 1 1

f

h

r

h

h

l

c

lo

Seeq

8003/5

1 0 0

————

—

———

—

1 0 1

————

—

———

—

1 1 0

————

—

———

—

1 1 1

————

—

———

PDN mode

r = rising edge clocks data

h = active high

c = RxC required continuously

f = falling edge clocks data

l = active low

n = RxC only during RxD transmission

m = RxC only during RxD transmission + 5 extra RxC cycles

* AMD mode is also recommended for all Motorola's QUICC, Power QUICC or simlar Communications Controllrs (MPC850, MPC860m ....). These controllers should be 5V or

3.3 V devices with 5V-friendly I/O pins