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ML4621 数据表(PDF) 3 Page - Micro Linear Corporation |
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ML4621 数据表(HTML) 3 Page - Micro Linear Corporation |
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3 / 8 page  ML4621 3 PIN DESCRIPTION (Pin Number in Parenthesis is for DIP Version) PIN NAME FUNCTION 1 (1) ECL LINK MON ECL link monitor output. Signal is low when the VIN+ and VIN– inputs exceed the minimum threshold set by a voltage on VTH ADJ. Signal is high when input signal level is below that threshold. 2 (2) TTL LINK MON TTL link monitor output. Same logic function as the ECL LINK MON. Capable of driving a 10mA LED indicator. This pin is normally tied to CMP ENABLE. 3 (3) CMP ENABLE Low voltage at this TTL input enables both the ECL and TTL outputs. A high TTL voltage disables the comparator output with ECL+ high, ECL– low, and TTL OUT high. 5 (4) VIN– This input should be capacitively coupled to the input source or to ground. (Input resistance is approximately 8k Ω). 6 (5) VIN+ This input should be capacitively coupled to the input source or to ground. (Input resistance is approximately 8k Ω). 8 (6) VDC An external capacitor on this pin integrates an error signal which nulls the offset of the input amplifier. If the DC feedback loop is not being used, this pin should be connected to VREF. 9 (7) CF2 A capacitor from this pin to ground controls the maximum bandwidth of the amplifier to accommodate lower operating frequencies. 10 (8) CF1 The capacitor on this pin should match the one on CF2. 11 (9) VOUT- Negative output of the amplifier, which is normally tied to CMP–. 12 (10) VOUT+ Positive output of the amplifier, which is normally tied to CMP+. 13 (11) CMP+ Comparator input pin. Open base configuration relies on the DC bias of the amp output to set proper DC operating voltage. Reestablish voltage if filtering is used between VOUT+ and CMP+. PIN NAME FUNCTION 14(12) CMP– Comparator input pin. Open base configuration relies on the DC bias of the amp output to set the proper DC operating voltage. Reestablish voltage if filtering is used between VOUT– and CMP–. 16(13) ECL– ECL comparator negative output. 17(14) ECL+ ECL comparator positive outout. 18(15) GND TTL Negative supply for the TTL comparator stage. If the TTL output is not necessary, connect GND TTL and VCC TTL to VCC. 19(16) VCC TTL Positive supply for the TTL comparator stage. If the TTL output is not necessary, connect GND TTL and VCC TTL to VCC. 20(17) TTL OUT TTL data output (totem pole type output stage). 21(18) GND Negative supply. Connect to – 5.2V for ECL operation, or to source ground for TTL operation. 22(19) VTH ADJ This input sets the minimum amplitude of the input signal required to cause the link monitors to go low. 23(20) VREF A 2.5V reference with respect to GND. 24(21) CPEAK A capacitor from this pin to GND determines the link monitor response time. 26(22) ISET Current into an internal diode connected between this pin and GND is turned around and pulled from CPEAK. This pin is normally connected to INOM. 27(23) INOM Sets a current of approximately 125µA when connected to ISET. 28(24) VCC Positive supply. Connect to source ground for ECL operation, or to 5V for TTL operation. |
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