ML4803

8

February 1999

Figure 4. Voltage Control Loop

60

40

20

0

–20

–40

–60

FREQUENCY (Hz)

0.1

10

1000

1

100

Power Stage

Overall Gain

Compensation

Network Gain

0

50

100

150

200

FREQUENCY (Hz)

0.1

1

10

1000

100

Power Stage

Overall

Compensation

Network

Figure 5. Voltage Loop Gain

Figure 6. Voltage Loop Phase

50

40

30

20

10

0

VEAO (V)

02

7

5

13

6

4

FF @ –55ºC

TYP @ –55ºC

TYP @ 155ºC

SS @ 155ºC

TYP @ ROOM TEMP

R

fC

COMP

COMP

=

´´ ´

1

2

p

(3)

R

Hz

nF

k

´´

=

1

628 30

16

330

.

W

C

f

R

ZERO

COMP

=

´´

´

1

2

10

p

(4)

C

Hz

k

F

´´

=

1

6 28 3

330

016

.

.

W

m

INTERNAL VOLTAGE RAMP

The internal ramp current source is programmed by way of

the VEAO pin voltage. Figure 7 displays the internal ramp

current vs. the VEAO voltage. This current source is used

to develop the internal ramp by charging the internal

30pF +12/–10% capacitor. See Figures 10 and 11. The

frequency of the internal programming ramp is set

internally to 67kHz.

PFC CURRENT SENSE FILTERING

In DCM, the input current wave shaping technique used

by the ML4803 could cause the input current to run away.

In order for this technique to be able to operate properly

under DCM, the programming ramp must meet the boost

inductor current down-slope at zero amps. Assuming the

programming ramp is zero under light load, the OFF-time

will be terminated once the inductor current reaches zero.

Subsequently the PFC gate drive is initiated, eliminating

the necessary dead time needed for the DCM mode. This

down the PFC. This situation is corrected by adding an

ML4803

ML4803

IVEAO

35µA

IOUT

VO

220µF

RLOAD

667

Ω

330k

Ω

11.3M

Ω

0.15µF

15nF

POWER

STAGE

COMPENSATION

VEAO

∆VEAO +

–