AR0230CS/D Rev. 8, Pub. 11/15 EN

8

©Semiconductor Components Industries, LLC, 2015.

AR0230CS: 1/2.7-Inch 2.1 Mp/Full HD Digital Image Sensor

Functional Overview

high dynamic range mode of operation where multiple images are combined on-chip to

produce a single image at 16-bit per pixel value. A compression mode is further offered

to allow the 16 bits per pixel to be transmitted to the host system as a 12-bit value with

close to zero loss in image quality.

Figure 2:

Typical Configuration: Serial Four-Lane HiSPi Interface

Notes:

1. All power supplies must be adequately decoupled.

2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for

slower two-wire speed.

3. The parallel interface output pads can be left unconnected if the serial output interface is used.

4. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply

are mounted as close as possible to the pad. Actual values and results may vary depending on lay-

out and design considerations. Refer to the AR0230CS demo headboard schematics for circuit rec-

ommendations.

5. ON Semiconductor recommends that analog power planes are placed in a manner such that cou-

pling with the digital power planes is minimized.

Master clock

(6–48 MHz)

SCLK

RESET_BAR

TEST

EXTCLK

Digital

ground

Analog

ground

Digital

Core

HiSPi

Analog

To

controller

From

controller

PLL

Digital

I/O

Analog

SLVSC_N

SLVSC_P

SLVS0_P

SLVS0_N

SLVS1_P

SLVS1_N

SLVS2_P

SLVS2_N

SLVS3_P

SLVS3_N

TRIGGER

OE_BAR

SHUTTER

FLASH