AR0331 datasheet(21/72 Pages) ONSEMI

21 / 72 page

AR0331_DS Rev. L Pub. 5/15 EN

©Semiconductor Components Industries, LLC, 2015.

AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor

Pixel Output Interfaces

Figure 11:

Timing Diagram

DLL Timing Adjustment

The specification includes a DLL to compensate for differences in group delay for each

data lane. The DLL is connected to the clock lane and each data lane, which acts as a

control master for the output delay buffers. Once the DLL has gained phase lock, each

lane can be delayed in 1/8 unit interval (UI) steps. This additional delay allows the user

to increase the setup or hold time at the receiver circuits and can be used to compensate

for skew introduced in PCB design.

Delay compensation may be set for clock and/or data lines in the hispi_timing register

R0x31C0. If the DLL timing adjustment is not required, the data and clock lane delay

settings should be set to a default code of 0x000 to reduce jitter, skew, and power dissipa-

tion.

Figure 12:

Block Diagram of DLL Timing Adjustment

….

MSB

LSB

TxPost

1 UI

TxPre

delay

data _lane 0

data _lane 1 clock _lane 0 data _lane 2 data _lane 3

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