LP621024E Series

128K X 8 BIT CMOS SRAM

(September, 2010, Version 1.0)

1

AMIC Technology, Corp.

Features

General Description

Single +5V power supply

Access times: 55/70 ns (max.)

Current:

Very low power version: Operating: 70mA (max.)

Standby:

25

μA (max.)

Full static operation, no clock or refreshing required

All inputs and outputs are directly TTL-compatible

Common I/O using three-state output

Output enable and two chip enable inputs for easy

application

Data retention voltage: 2V (min.)

Available

in

32-pin

SOP,

TSOP

and

TSSOP

(8 X 13.4mm) packages

Pb-Free package only

All Pb-free (Lead-free) products are RoHS compliant

The LP621024E is a low operating current 1,048,576-bit

static random access memory organized as 131,072 words

by 8 bits and operates on a single 5V power supply.

Inputs and three-state outputs are TTL compatible and

allow for direct interfacing with common system bus

structures.

Two chip enable inputs are provided for POWER-DOWN

and device enable and an output enable input is included

for easy interfacing.

Data retention is guaranteed at a power supply voltage as

low as 2V.

Product Family

Power Dissipation

Product Family

Operating

Temperature

VCC

Range

Speed

Data Retention

Standby

Operating

Package Type

LP621024E

0

°C ~ +70°C

4.5V~5.5V

55ns / 70ns

0.5

μA

2

μA

10mA

32L SOP

/TSOP/TSSOP

°C and not 100% tested.

2. Data retention current VCC = 2.0V.

Pin Configurations

SOP

TSOP/(TSSOP)

NC

A16

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

GND

A10

A9

A8

A13

CE2

A15

VCC

A11

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

OE

CE1

WE

1

16

17

32

Pin No.

Pin

Name

Pin No.

Pin

Name

12

A9

3

4

5

6

7

8

9

10

11

12

13

14

30

29

28

27

26

25

24

22

19

21

20

23

18

17

A8

A13

CE2

A15

VCC

NC

A16

A14

A12

A7

A6

A3

A2

A1

A0

GND

A11

WE

CE1

15

16

31

32

A5

A4

A10

OE