SN74LS161AM datasheet(2/8 Pages) ONSEMI

2 / 8 page

SN74LS161A, SN74LS163A

http://onsemi.com

CONNECTION DIAGRAM DIP (TOP VIEW)

Parallel Enable (Active LOW) Input

Parallel Inputs

Count Enable Parallel Input

Count Enable Trickle Input

Clock (Active HIGH Going Edge) Input

Master Reset (Active LOW) Input

Synchronous Reset (Active LOW) Input

Parallel Outputs

Terminal Count Output

P0 − P3

CEP

CET

Q0 − Q3

1.0 U.L.

0.5 U.L.

1.0 U.L.

0.5 U.L.

1.0 U.L.

10 U.L.

0.5 U.L.

0.25 U.L.

0.5 U.L.

0.25 U.L.

0.5 U.L.

5 U.L.

NOTES:

a) 1 TTL Unit Load (U.L.) = 40

mA HIGH/1.6 mA LOW.

HIGH

LOW

(Note a)

PIN NAMES

VCC = PIN 16

GND = PIN 8

LOGIC SYMBOL

NOTE:

The Flatpak version has the same

pinouts (Connection Diagram) as

the Dual In-Line Package.

12345

VCC

CET

CEP GND

934

14 131211

PE P0 P1 P2 P3

CEP

CET

*R Q0 Q1 Q2 Q3

*MR for LS161A

*SR for LS163A

*MR for LS161A

*SR for LS163A

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