LC79451KB

No.A2223-13/38

6-1-1. I

in sequence. The address without the register allocation is skipped.

6-1-2. I

each address are read from registers in sequence. The address without the register allocation is skipped.

When the register data of each address are less than 8 bits, the data of the remaining bit are read in “0.”

In read image data, last bit is old (past) image data, and one high rank bit is new (current) image data.

6-1-3. I

During the period when SCL line is "H", the change of SDA line from “H” to “L” is recognized to be START

condition, and the change of SDA line from “L” to “H” is recognized to be STOP condition. The master device on the

system can communicate with a particular slave device by sending the device ID of 7 bits long and instruction codes

of 1 bit long as read “1”/write “0” on SDA line following START condition.

When the device ID of the master device accords with the device ID of the slave device, the slave device replies to

SDA line with the acknowledge (ACK), and Read or Write operates according to Read/Write command code. The

device is set to standby mode when device ID does not accord.

SDA line is changeable while SCL line is “L”.

SDA line transfers the consecutive 8 bits from the master device. And SDA line is opened in the ninth clock cycle

period. The slave device which receives data on the system bus sends low to SDA line. Sending low is the

acknowledge signal indicating that data has been received.

The command data is comprised of address 8 bits and data 8 bits. The command data is stored by the rising of SCL

line in the acknowledge period after having received the data 8 bits.

6-1-4. I

bits and the slave address of 3 bits. Upper 2 bits of the slave address is settable with ID1 pin, and ID2 pin. Please

connect ID1 pin and ID2 pin to VDD or VSS.

Write ”0”

⇒ connect to VSS

Read ”1”

⇒ connect to VDD

0

1

ID1

ID2

R/W

0

1

1

MSB

LSB

Device ID

Device Cord

Slave Address

W shows R/W = 0

START

condition

ACK

Register address (N)

•••

Register data (N)

Register data (N+1)

ACK

ACK

ID + W

R shows R/W = 1

ACK

Register address (N)

ACK

ID + W

ACK

Register data (N)

•••

Register data (N+1)

Register data (N+2)

ACK

ACK

ID + R

START

condition

START

condition

A7

A4

A1

A6 A5

A3 A2

A0

D7

D4

D1

D6 D5

D3 D2

D0

SCL

SDA

(Internal latch signal)

ACK

ACK

D7

ACK

ID6

ID3

ID0

ID5 ID4

ID2 ID1

RW