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SM5838AS 数据表(PDF) 8 Page - Nippon Precision Circuits Inc |
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SM5838AS 数据表(HTML) 8 Page - Nippon Precision Circuits Inc |
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8 / 14 page ![]() SM5838AS NIPPON PRECISION CIRCUITS—8 Output Enable When OE is HIGH, DOUT0 to DOUT7 become high impedance. Note that because RE operation is inde- pendent of OE operation, the read address pointer can be incremented even when the outputs are high impedance. TYPICAL APPLICATIONS Note that at power-ON, the write address pointer and read address pointer positions are undefined. Accordingly, RW and RR reset cycles are required. 1H Delay Line A 5120-word delay line can be realized by perform- ing simultaneous write reset and read reset at power- ON. An n-word delay line (21 to 5210-word) can be real- ized using any of the following methods. ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, RR="H" ,RE="L" CKW t OES t OES t OZ t ZO t A t A t OEH t OEH t CKW t CLK DOUT OE Hi-Z (n-1) (n) (n+3) n cycle n+3 cycle n+2 cycle n+1 cycle 1. Perform reset in sync with desired delay length. 2. Stagger RW and RR timing to desired delay length. 3. Manipulate the write or read address pointer using WE or RE to disable incrementing to maintain sync with desired delay length. 1H (5120-word) delay line timing ,,,,,,,,, ,,,,,,,,, ,,,,,,,,, ,,,,,,,,, ,,,,,,,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,, ,, ,, ,, ,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,,, ,, ,, ,, ,, ,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, RS t RH t DS t DH t A t OH t CLK 1H WE="L" , RE="L" , OE="L" RW RR DIN DOUT 2H 0 cycle 2 cycle 1 cycle 5120+0 cycle 5119 cycle 5120+1 cycle 5120+3 cycle 5120+2 cycle 0 5119 5118 3 2 1 0 1 2 3 0 1 2 5120 cycle |
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