ASM705, ASM706, ASM707, ASM708, ASM813L

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Detailed Description

A proper reset input enables a microprocessor /

microcontroller to start in a known state. ASM70X and

ASM813L assert reset to prevent code execution errors

during power−up, power−down and brown−out conditions.

RESET/RESET Timing

The RESET/RESET signals are designed to start a

mP/mC

in a known state or return the system to a known state.

The ASM707/708 have two reset outputs, one

active−HIGH RESET and one active−LOW RESET output.

The ASM813L has only an active−HIGH output. RESET is

simply the complement of RESET.

During a power−up sequence, RESET remains low until

the supply rises above the threshold level, either 4.65 V or

4.40 V. RESET goes high approximately 200 ms after

crossing the threshold.

below the threshold level and is guaranteed to be under 0.4 V

threshold level, RESET pulses low. If a brown−out occurs

during an already initiated reset, the pulse will continue for

a minimum of 140 ms.

Power Failure Detection with Auxiliary Comparator

All devices have an auxiliary comparator with 1.25 V trip

point and uncommitted output (PFO) and noninverting input

(PFI). This comparator can be used as a supply voltage

monitor with an external resistor voltage divider. The

attenuated voltage at PFI should be set just below the 1.25

threshold. As the supply level falls, PFI is reduced causing

the PFO output to transit LOW. Normally PFO interrupts the

processor so the system can be shut down in a controlled

manner.

Figure 3. WDI Three−state Operation

Manual Reset (MR)

The active−LOW manual reset input is pulled high by a

250

mA pull−up current and can be driven low by

CMOS/TTL logic or a mechanical switch to ground. An

external debounce circuit is unnecessary since the 140 ms

minimum reset time will debounce mechanical pushbutton

switches.

By connecting the watchdog output (WDO) and MR, a

watchdog timeout forces RESET to be generated. The

ASM813L should be used when an active−HIGH RESET is

required.

Watchdog Timer

The watchdog timer available on the ASM705/706/813L

monitors

mP/mC activity. An output line on the processor is

used to toggle the WDI line. If this line is not toggled within

1.6 seconds, the internal timer puts the watchdog output,

WDO, into a LOW state. WDO will remain LOW until a

toggle is detected at WDI.

If WDI is floated or connected to a three−stated circuit, the

watchdog function is disabled, meaning, it is cleared and not

counting. The watchdog timer is also disabled if RESET is

asserted. When RESET becomes inactive and the WDI input

sees a high or low transition as short as 50 ns, the watchdog

timer will begin a 1.6 second countdown. Additional

transitions at WDI will reset the watchdog timer and initiate

a new countdown sequence.

WDO will also become LOW and remain so, whenever

threshold. There is no minimum pulse width for WDO as

there is for the RESET outputs. If WDI is floated, WDO

essentially acts as a low−power output indicator.

Figure 4. Watchdog Timing