ASM705, ASM706, ASM707, ASM708, ASM813L

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Table 1. PIN DESCRIPTION

Pin Number

ASM705/706

ASM707/708

ASM813L

DIP/

SO

MicroSO

DIP/

SO

MicroSO

DIP/

SO

MicroSO

Name

Function

1

3

1

3

1

3

MR

Manual reset input. The active LOW input triggers a

reset pulse. A 250 mA pull−up current allows the pin

to be driven by TTL/CMOS logic or shorted to

ground with a switch.

2

4

2

4

2

4

+5 V power supply input.

3

5

3

5

3

5

GND

Ground reference for all signals.

4

6

4

6

4

6

PFI

Power−fail input voltage monitor. With PFI less than

1.25 V, PFO goes LOW. Connect PFI to Ground or

5

7

5

7

5

7

PFO

Power−fail output. The output is active LOW and

sinks current when PFI is less than 1.25 V.

6

8

−

−

6

8

WDI

Watchdog input. WDI controls the internal watchdog

timer. A HIGH or LOW signal for 1.6 sec at WDI

allows the internal timer to run−out, setting WDO

LOW. The watchdog function is disabled by floating

WDI or by connecting WDI to a high impedance

three−state buffer. The internal watchdog timer

clears when: RESET is asserted; WDI is three−

stated; or WDI sees a rising or falling edge.

−

−

6

8

−

−

NC

Not Connected.

7

1

7

1

−

−

RESET

Active LOW reset output. Pulses LOW for 200 ms

below the reset threshold. RESET remains LOW for

MR goes from LOW to HIGH. A watchdog timeout

will not trigger RESET unless WDO is connected to

MR.

8

2

−

−

8

2

WDO

Watchdog output. WDO goes LOW when the 1.6

second internal watchdog timer times−out and does

not go HIGH until the watchdog is cleared. In addi-

WDO goes LOW. Unlike RESET, WDO does not

exceeds the reset threshold, WDO goes HIGH with

no delay.

−

−

8

2

7

1

RESET

Active HIGH reset output. The inverse of RESET.

The ASM813L only has a RESET output.