MT9044

Advance Information

2

Figure 2 - Pin Connections

Pin Description

Pin #

PLCC

Pin #

MQFP

Name

Description

1,10,

23,31

39,4,17

,25

Ground. 0 Volts.

2

40

TCK

Test Clock (TTL Input): Provides the clock to the JTAG test logic. This pin is

341

TCLR

TIE Circuit Reset (TTL Input): A logic low at this input resets the Time Interval

Error (TIE) correction circuit resulting in a re-alignment of input phase with output

phase as shown in Figure 19. The TCLR pin should be held low for a minimum of

300ns. This pin is internally pulled down to VSS.

442

TRST

Test Reset (TTL Input): Asynchronously initializes the JTAG TAP controller by

putting it in the Test-Logic-Reset state. This pin is internally pulled down to VSS.

543

SEC

Secondary Reference (TTL Input). This is one of two (PRI & SEC) input

reference sources (falling edge) used for synchronization. One of three possible

frequencies (8kHz, 1.544MHzMHz, or 2.048MHz) may be used. The selection of

the input reference is based upon the MS1, MS2, LOS1, LOS2, RSEL, and GTi

6

44

PRI

Primary Reference (TTL Input). See pin description for SEC. This pin is

7,28

1,22

8

2

OSCo

Oscillator Master Clock (CMOS Output). For crystal operation, a 20MHz crystal

is connected from this pin to OSCi, see Figure 10. For clock oscillator operation,

this pin is left unconnected, see Figure 9.

9

3

OSCi

Oscillator Master Clock (CMOS Input). For crystal operation, a 20MHz crystal is

connected from this pin to OSCo, see Figure 10. For clock oscillator operation, this

pin is connected to a clock source, see Figure 9.

11

5

F16o

Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8kHz 61ns active

low framing pulse, which marks the beginning of an ST-BUS frame. This is typically

used for ST-BUS operation at 8.192 Mb/s. See Figure 20.

1

8

7

43

9

10

11

12

37

33

34

35

36

38

39

40

41

42

VDD

OSCo

OSCi

F16o

F0o

F8o

C1.5o

GTi

GTo

LOS2

LOS1

MS2

MS1

RSEL

18 19 20 21 22 23 24

MT9044

2

5

643

44

32

31

30

29

25 26 27 28

13

14

15

16

17

TEST

VSS

TDO

AVDD

TSP

RSP

VSS

HOLDOVER

39

2

1

42 41

3

4

5

6

31

27

28

29

30

32

33

34

35

36

VDD

OSCo

OSCi

F16o

F0o

F8o

C1.5o

GTi

GTo

LOS2

LOS1

MS2

MS1

RSEL

12 13 14 15 16 17 18

MT9044AL

40

43

44

37

38

26

25

24

19 20 21 22

7

8

9

10

11

HOLDOVER

TEST

VSS

TDO

AVDD

TSP

RSP

VSS

23