LSI

LS3201

3

3. RAM

The system has 80x4bit of program RAM with IO address as follows.

Address

Status

Description

Initialize

0-13H

R/W

RAM

undefined

14H-1fH

R/W

Display RAM

undefined

20-2fH

R/W

RAM

undefined

30H

R/W

rptrl

undefined

31H

R/W

rptrh

undefined

32H

R/W

rptr1h

undefined

33H

R/W

Beep Control

0

34H-3fH

R/W

RAM

Undefined

50H-53H

R/W

RAM

Undefined

54H-5fH

R/W

Display RAM

Undefined

70H

W

Tone Data Low

Undefined

70H

R

Tone Data Low Value

Undefined

71H

W

Tone Data High

Undefined

71H

R

Tone Data High Value

Undefined

72H

W

Tone Control Register

0

72H

R

Tone Status

0

73H

W

IO Register

0

73H

R

Timer 1

0

74H

W

Tone 2 Control

0

75H

W

Tone frequency control

0

76H

W

FPC Control

0

76H

R

Timer 2 Control

0

77H

W

FIO Control

Address 31H:30H forms a 8 bit address for indirect read/write operation.

Address 32H:30H forms a 8 bit address for indirect read/write operation.

Address 1H:0H forms a 8bit address for indirect read/write operation for pointer read/write.

Address 3H:2H forms a 8bit address for indirect read/write operation for pointer1 read/write.

Indirect address is specified, for example, as rINC #op

Indirect Operand (#op)

Resulting address

#0

RptrH.RptrL

#1

Rpt1H.RptrL