| 数据搜索系统,热门电子元器件搜索 |
|
MT9126AS 数据表(PDF) 2 Page - Mitel Networks Corporation |
|
|
|||||||||||||||||||||||||||||
MT9126AS 数据表(HTML) 2 Page - Mitel Networks Corporation |
|
2 / 22 page ![]() MT9126 Preliminary Information 8-34 Figure 2 - Pin Connections Pin Description Pin # Name Description 1 EN1 Enable Strobe 1 (Output). This 8 bit wide, active high strobe is active during the B1 PCM channel in ST-BUS mode. Becomes a single bit, high true pulse when LINEAR=1. In SSI mode this output is high impedance. 2 MCLK Master Clock (input). This is a 4.096 MHz (minimum) input clock utilized by the transcoder function; it must be supplied in both ST-BUS and SSI modes of operation. In ST-BUS mode the C4 ST-BUS clock is applied to this pin. This synchronous clock is also used to control the data I/O flow on the PCM and ADPCM input/output pins according to ST-BUS requirements. In SSI mode this master clock input is derived from an external source and may be asynchronous with respect to the 8 kHz frame. MCLK rates greater than 4.096 MHz are acceptable in this mode since the data I/O rate is governed by BCLK. 3F0i Frame Pulse (Input). Frame synchronization pulse input for ST-BUS operation. SSI operation is enabled by connecting this pin to VSS. 4 C2o 2.048 MHz Clock (Output). This ST-BUS mode bit clock output is the MCLK (C4) input divided by two, inverted, and synchronized to F0i. This output is high-impedance during SSI operation. 5 BCLK Bit Clock (Input). 128 kHz to 4096 kHz bit clock input for both PCM and ADPCM ports; used in SSI mode only. The falling edge of this clock latches data into ADPCMi, PCMi1 and PCMi2. The rising edge clocks data out on ADPCMo, PCMo1 and PCMo2. This input must be tied to VSS for ST-BUS operation. 6 PCMo1 Serial PCM Stream 1 (Output). 128 kbit/s to 4096 kbit/s serial companded/linear PCM output stream. Data are clocked out by rising edge of BCLK in SSI mode. Clocked out by MCLK divided by two in ST-BUS mode. See Figure 14. 7 PCMi1 Serial PCM Stream 1 (Input). 128 kbit/s to 4096 kbit/s serial companded/linear PCM input stream. Data are clocked in on falling edge of BCLK in SSI mode. Clocked in at the 3/4 bit position of MCLK in ST-BUS mode. See Figure 14. 8VSS Digital Ground. Nominally 0 volts. 9 LINEAR Linear PCM Select (Input). When tied to VDD the PCM I/O ports (PCM1,PCM2) are 16- bit linear PCM. Linear PCM operates only at a bit rate of 2048 kbit/s. Companded PCM is selected when this pin is tied to VSS. See Figures 5 & 8. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 MS1 VDD MS3 IC MS4 FORMAT MS2 PWRDN ADPCMi ADPCMo MS5 MS6 EN2 PCMo1 BCLK PCMi1 LINEAR ENB2/F0od VSS C2o MCLK F0i PCMi2 ENB1 PCMo2 EN1 SEL A/ µ |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |