MT9196AS datasheet(2/38 Pages) MITEL

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MT9196

Preliminary Information

7-128

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

1M-

Inverting Microphone (Input). Inverting input to microphone amplifier from the handset

microphone.

2M+

Non-Inverting Microphone (Input). Non-inverting input to microphone amplifier from the

handset microphone.

3VBias

Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external amplifiers.

Connect 0.1 µF capacitor to VSSA.

4VRef

Reference voltage for codec (Output). Nominally [(VDD/2)-1.5] volts. Used internally.

Connect 0.1 µF capacitor to VSSA.

PWRST

Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low).

6IC

Internal Connection. Tie externally to VSS for normal operation.

7VSSD

Digital Ground. Nominally 0 volts.

8CS

Chip Select (Input). This input signal is used to select the device for microport data

transfers. Active low. TTL level compatible.

9SCLK

Serial Port Synchronous Clock (Input). Data clock for microport. TTL level compatible.

DATA1

Bidirectional Serial Data. Port for microprocessor serial data transfer. In Motorola/National

mode of operation, this pin becomes the data transmit pin only and data receive is

performed on the DATA2 pin. TTL level compatible input levels.

DATA2

Serial Data Receive. In Motorola/National mode of operation, this pin is used for data

receive to the IDPC. In Intel mode, serial data transmit and receive are performed on the

DATA1 pin and DATA2 is disconnected. Input level TTL compatible.

Watchdog (Output). Watchdog timer output. Active high.

IRQ

Interrupt Request (Open Drain Output). Low true interrupt output to microcontroller.

Dout

Data Output. A tri-state digital output for 8 bit wide channel data being sent to the Layer 1

device. Data is shifted out via this pin concurrent with the rising edge of BCL during the

timeslot defined by STB, or according to standard ST-BUS timing.

Din

Data Input. A digital input for 8 bit wide channel data received from the Layer 1 device.

Data is sampled on the falling edge of BCL during the timeslot defined by STB, or according

to standard ST-BUS timing. Input level is CMOS compatible.

AUXin

MIC+

VDD

HSPKR-

HSPKR+

SPKR-

SPKR+

VSS SPKR

AUXout

VSSA

STB/F0i

CLOCKin

XSTAL2

Din

M-

M+

VBias

VRef

PWRST

VSSD

SCLK

DATA1

DATA2

IRQ

Dout

28 PIN PLCC

28 PIN SOIC/PDIP

PWRST

VSSD

SCLK

DATA1

DATA2

VDD

HSPKR-

HSPKR+

SPKR-

SPKR+

VSS SPKR

AUXout

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