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PDSP16488AC 数据表(PDF) 8 Page - Mitel Networks Corporation |
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PDSP16488AC 数据表(HTML) 8 Page - Mitel Networks Corporation |
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8 / 33 page  8 1024 1024 1024 1024 4 4 OR 8 4 ARRAY IP7:0 ODD FIELD Output is shifted by 1 line in every field FIELD DELAY VIDEO LINE N 2 L7:0 N 1 N 1 N L7:0 512 512 512 512 8 8 ARRAY 512 512 512 512 IP7:0 FIELD DELAY Output is shifted by 1 line in every field ODD FIELD DELAY BYPASSED REG B BIT 7 SET VIDEO LINE N 2 N 1 N 1 N 2 N N 2 L7:0 512 512 512 512 8 8 ARRAY 512 512 512 512 IP7:0 FIELD DELAY Output is shifted by 2 lines in every field ODD FIELD DELAY BYPASSED REG B BIT 7 SET VIDEO LINE N 4 N 3 N 1 N 4 N N 2 N 1 N 3 N 2 C24 C56 C16 C48 C8 C40 C0 C32 LINE N 3 LINE N 2 LINE N 1 LINE N LINE N 1 LINE N 2 LINE N 3 LINE N 4 C25 C57 C17 C49 C9 C41 C1 C33 C26 C58 C18 C50 C10 C42 C2 C34 C27 C59 C19 C51 C11 C43 C3 C35 C28 C60 C20 C52 C12 C44 C4 C36 C29 C61 C21 C53 C13 C45 C5 C37 C30 C62 C22 C54 C14 C46 C6 C38 C31 C63 C23 C55 C15 C47 C7 C39 8 8 WINDOW C48 C8 C40 C0 C32 LINE N 2 LINE N 1 LINE N LINE N 1 LINE N 2 C49 C9 C41 C1 C33 C50 C10 C42 C2 C34 C51 C11 C43 C3 C35 C52 C12 C44 C4 C36 5 5 WINDOW C4 C8 C0 LINE N 1 LINE N LINE N 1 C5 C9 C1 C6 C10 C2 3 3 WINDOW Fig. 5 Line delay allocations in SINGLE device interlaced systems |
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