PDSP16488A MA

3

TYPE

INPUT

I/O

INPUT

INPUT

DUAL

FUNCTION

OUTPUT

OUTPUT

INPUT

OUTPUT

I/O

INPUT

INPUT

I/O

INPUT

OUTPUT

OUTPUT

INPUT

INPUT

INPUT

INPUT

OUTPUTS

OUTPUTS

SUPPLY

DESCRIPTION

Pixel data input to the first line delay. [most significant byte in 16 bit mode]

Pixel data input to the second group of line delays. [least significant byte in 16bit mode]. Alternatively

an output from the last line delay when the appropriate mode bit is set.

The first line delay in the first group is bypassed when this input is active. (High). No internal pull up.

Resets the line delay address pointers when high. Normally the composite sync signal in real time

applications. In non real time systems it defines a frame store update period, when low.

Address/data connections from a MASTER or SINGLE device to the external coefficient source, with

X15 defining EPROM or Host support. Otherwise they provide the expansion data input.

Signed 16 bit scaled data or multiplexed 32 bit intermediate data. During intermediate transfers the

most significant half is valid when the clock is low, and the least significant half when clock is high.

During programming a MASTER device outputs a timing strobe on this pin. This is passed down the

chain in a multiple device system, using the

PC0 input on the next device.

This pin is used in conjunction with

PC1 in multiple device systems. It terminates the write strobe from

a MASTER device which is EPROM supported.

This output provides a version of the HRES input which has been delayed by an amount defined by

the user.

The data strobe from a host computer. Active low. This pin will be an output from an EPROM supported

MASTER device which provides strobes to the remaining devices.

An active low enable which is internally gated with R/

W and DS to perform reads or writes to the

internal registers. In a SINGLE or MASTER device, which is supported from an EPROM, the bottom

72 addresses are always used and CE is not needed.

CE can then be used to initiate a new register

load sequence after the power on load sequence.

Read / not write line from the host CPU. When an EPROM is used this pin should be tied low.

This pin is normally an input which signifies that registers are to be changed or examined. It is,

however, an output from an EPROM supported SINGLE or MASTER device indicating to the rest of

the system that registers are being updated.

Clock. All events are triggered on the rising edge of the clock, except the latching of least significant

expansion inputs . Internally the clock can be multiplied by two or four in order to increase the effective

number of multipliers.

This output indicates the result from the internal comparison. A high value indicates that the pixel

was greater than the internal threshold. The output is only valid from the last device in a chain.

When high this output indicates that there has been a gain control overflow.

Active low power on reset signal.

Tied to ground to indicate a SINGLE device system. Internal pull up resistor.

Tied to ground to indicate the MASTER device in a multiple device system. Must be left open circuit

in a SINGLE device system. Internal pull up.

Output enable signal. Active low.

Four address bits from a MASTER specifying one of sixteen devices in a multiple device system. Must

be externally decoded to provide chip enables for the additional devices.

These bits indicate the field selection given by the auto select logic. The same coding as that used

for Control Register bits C5:4 is used.

Four Power and ground pairs. All must be connected.

NAME

IP7:0

L7:0

BYPASS

HRES

X15:0

D15:0

PC1

PC0

DELOP

DS

CE

R/ W

PROG

CLK

BIN

OV

RES

SINGLE

MASTER

OEN

CS3:0

F1:0

VCC / GND