PDSP16488GC datasheet(15/33 Pages) MITEL

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BIT 7

This bit controls the bypass option on the first line

delay on the L7:0 inputs. It is only effective when an

8 bit pixel mode is selected, which also needs more

than four line delays. When L7:0 are used as outputs

it should always be reset. In the 16-bit modes the

bypass function is only controlled by the BYPASS pin,

and the bit is redundant.

Function

Second line delay group fed from the

first group

Second line delay group fed from L7:0

which become inputs

Store pixels to end of line

Store pixels till count is reached

Frame store operation

Not Used

No delays on pixel inputs

4 delays on both pixel inputs

Use expansion adder

Expansion adder disabled

Not used

Use first delay in second group

Bypass first delay in second group

Bit

2:1

6:5

Code

BIT 0

If this bit is set, the 20-bit field selected from the 32-bit

result, is defined automatically by internal logic.

BITS 3:1 These bits are in conjunction with register D, bits 7:5

to define the pixel delay from the HRES input to the

DELOP output. They are used to match the appropri-

ate processing delay in a particular system. The

minimum delay is 29 pixel clocks.

BITS 5:4 These bits define which of the four 20-bit fields out of

the 32-bit final result is selected as the input to the gain

control. They are redundant when the gain control is

not used, or if register C, bit 0, is set.

BITS 7:6 These bits define the use of the gain control as given

in Table 10. Intermediate devices in a multiple device

systemmust bypass the gain control block, otherwise

the additional pipeline delays will affect the result.

Disabling the gain control block will reduce the device

pipeline by 13 CLK cycles from the delays shown in

Table 6.

Table 9 Register B bit functions

Table 10 Register C bit functions (continues…)

Function

Field selection defined by C5:4

Automatic field selection

DELOP = 29 0 clocks

DELOP = 29 8 clocks

DELOP = 29 16 clocks

Code

000

001

010

Bit

3:1

Function

DELOP = 29 24 clocks

DELOP = 29 32 clocks

DELOP = 29 40 clocks

DELOP = 29 48 clocks

DELOP = 29 56 clocks

Select upper 20 bits

Select next 20 bits

Select bottom 20 bits

By-pass the gain control

Normal gain control output

Saturate at max. ve and

ve values.

Force

ve to zero.Sat. ve values.

Code

011

100

101

110

111

Bit

3:1

5:4

7:6

Table 10 Register C bit functions (continued)

Table 11 Register D bit functions

BIT 0

If this bit is set the expansion data input is delayed

by four pixel clocks before it is added to the present

convolver output. It is used in multiple device systems

when the partial window width is 8 pixels.

BIT 1

When this bit is set the internal sum is shifted to the

left by 8 places before being added to the expansion

input. It is used when two devices are used, each in an

8-bit pixel mode, to construct a 16-bit pixel mode.

BITS 3:2 These bits define the delays on both sets of pixel

inputs before entering the line stores. The delays are

always identical on both sets.

BIT 4

When this bit is set the convolver interprets 8 or 16-

bit pixels as 2’s complement signed numbers

BIT 7:5

These bits add 0 to 7 additional clock delays to those

selected by Register C, bits 3:1.

Function

X15:0 Not delayed

X15:0 Delayed

Internal sum not shifted

Internal sum multiplied by 256

Input to line stores not delayed

Input to line stores delayed by 4

Input to line stores delayed by 8

Input to line stores delayed by 12

Unsigned pixel data input

2’s complement pixel data input

Add 0 to 7 clock delays to DELOP

Bit

3:2

7:5

Code

XXX

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