3

SP8713

OPERATING NOTES

The RF inputs are biased internally and are normally coupled to the signal source with suitable capacitors.

The output stage has a novel design and is intended to drive a CMOS synthesiser input. External pull-down resistors or

circuits are not required. The SP8713 is not suitable for driving TTL or similar devices.

The device will operate down to DC frequencies for non-sinusoidal signals provided that the input slew rate is better than

100V/

µs.

POWER DOWN (pin 7) is connected internally to a pull-up resistor. If the battery economy facility is not used, pin 7 should

Fig. 4 Modulus control timing diagram

RF INPUT

CLOCK

MODULUS

CONTROL

INPUTS

OUTPUT

t s

t h

32 or 36

32, 33 or 36

DON'T CARE

DON'T CARE

Fig. 3 Typical input characteristics

Modulus

Modulus

Division

Control 1

Control 2

Ratio

(Pin 3)

(Pin 6)

LL

65

HL

64

HH

72

LH

72

TYPICAL

SENSITIVITY

TYPICAL

OVERLOAD

1000

800

600

400

200

0

200

400

600

800

1000

1200

* Tested as specified in table of Electrical Characteristics

FREQUENCY (MHZ)

GUARANTEED*

OPERATING WINDOW

Table 1 Truth table