SM5877AM datasheet(13/16 Pages) NPC

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SM5877AM

NIPPON PRECISION CIRCUITS—13

FUNCTIONAL DESCRIPTION

System Clock/Speed Switching (XTI, XTO, CKO, DS)

Note that the input clock accuracy and signal-to-

noise ratio greatly inﬂuence the AC analog character-

istics. Accordingly, care should be taken to ensure

that the clock is free from jitter.

The system clock can be controlled by a crystal

oscillator comprising a crystal connected between

XTI and XTO and the built-in CMOS inverter. Alter-

natively, an external system clock can be input on

XTI. As the internal CMOS inverter has a feedback

resistor, the external clock can be AC coupled to

XTI. The system clock is output on CKO.

System Reset (RSTN)

The device should be reset in the following cases.

At power ON

When LRCI and/or the system clock XTI stop, or

other abnormalities occur.

The system clock on XTI can be set to run at one of

two speeds, 384fs (normal speed) or 192fs (double-

speed), where fs is the input frequency on LRCI. The

speed for CD playback is set by the input level on

DS, as shown in table 1. The system clock should be

ﬁxed at 16.9344 MHz.

Table 1. System clock select

Parameter

Symbol

LOW

(normal

speed)

HIGH

(double

speed)

XTI input clock

frequency

fXI

(= 1/tXI)

384fs

192fs

CD playback

XTI frequency

fXI

16.9344 MHz

at fs = 44.1

kHz

16.9344 MHz

at fs = 88.2

kHz

CKO output

clock frequency

fCO

384fs

192fs

Internal system

clock period

TSYS

tXI

The device is reset by applying a LOW-level pulse on

RSTN. At system reset, the internal arithmetic opera-

tion and output timing counter are synchronized on

the next LRCI rising edge, as shown in ﬁgure 1.

Audio Data Input (DI, BCKI, LRCI)

The digital audio data is input on DI in MSB-ﬁrst, 2s-

complement, 16-bit serial format.

Serial data bits are read into the SIPO register (serial-

to-parallel converter register) on the rising edge of the

bit clock BCKI.

The arithmetic operation and output timing are inde-

pendent of the input timing. Accordingly, after a reset,

Figure 1. System reset timing

RSTN

Internal reset

Outputs muted

LRCI

LOW

as long as the clock frequency ratio between LRCI

and the system clock XTI is maintained, phase dif-

ferences between LRCI, BCKI and the system clock

XTI do not affect the functional operation. Also, any

jitter present on the data input clock does not appear

as output pulse jitter.

The bit clock frequency on BCKI should be between

32fs and 64fs.

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