TLV5604

2.7-V TO 5.5-V 10-BIT 3-

µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176B – DECEMBER 1997 – REVISED JULY 2002

7

POST OFFICE BOX 655303

electrical characteristics over recommended operating free-air temperature range

(unless otherwise noted) (continued)

digital input timing requirements

MIN

NOM

MAX

UNIT

tsu(CS–FS)

Setup time, CS low before FS

↓

10

ns

tsu(FS–CK)

Setup time, FS low before first negative SCLK edge

8

ns

tsu(C16–FS)

Setup time, sixteenth negative SCLK edge after FS low on which bit D0 is sampled before

rising edge of FS

10

ns

tsu(C16–CS)

Setup time. The first positive SCLK edge after D0 is sampled before CS rising edge. If FS

is used instead of the SCLK positive edge to update the DAC, then the setup time is between

the FS rising edge and CS rising edge.

10

ns

twH

Pulse duration, SCLK high

25

ns

twL

Pulse duration, SCLK low

25

ns

tsu(D)

Setup time, data ready before SCLK falling edge

8

ns

th(D)

Hold time, data held valid after SCLK falling edge

5

ns

twH(FS)

Pulse duration, FS high

20

ns

PARAMETER MEASUREMENT INFORMATION

12

3

4

5

15

16

D15

D14

D13

D12

D1

D0

tsu(FS-CK)

tsu(CS-FS)

twH(FS)

th(D)

tsu(D)

twH

twL

tsu(C16-CS)

tsu(C16-FS)

SCLK

DIN

CS

FS

Figure 1. Timing Diagram