TM1IO datasheet(11/25 Pages) PANASONIC

11 / 25 page

MN103SFM9K

32-bit Single-chip Microcontroller

Publication date: August 2014

PubNo. 232M9-010E

1.3.3

Pin Functions

Table:1.3.2 Pin Functions

Name

TQFP 48

Pin No.

I/O

Other Function

Function

Description

VDD

Power supply pin

Power pin for 5 V, digital IO.

Apply 5 V to all of pins and connect capacitor

of over 10

μF between all of the VDD and

VSS pins. (allocate near the pins)

It is recommended that total capacitance

between all of the VDD and VSS is more than

10-times capacitance between all of the

VDD2 and VSS.

VDD2

Power supply pin

Power pin for 1.8 V, digital IO

Connect capacitor of over 1

μF between all of

the VDD2 and VSS pins.

(allocate near the pins)

VSS

Power supply pin

GND for digital

VPPEX

Power supply pin

Power for flash EEPROM

Connect with VDD.

OSC1

OSC0

input

output

Clock input pin

Clock output pin

Extend ceramic or crystal oscillators or input

a clock to OSC1.

NRST

input

Reset pins

(negative logic)

This pin resets the chip when power is turned

on and contains an internal pull-up resistor.

Setting this pin “L” level initialize the internal

state of the device. Thereafter, setting the

input to “H” level releases the reset. The

hardware waits for the system clock to

stabilize, then processes the reset interrupt.

Connect capacitor of over 0.1

μF between

NRST and VSS pins.

P10

P11

P12

P13

P14

P15

P16

P17

I/O

IRQ04/ EXTRG0

IRQ05/ EXTRG1

IRQ06

IRQ07

IRQ08

TM6IO

TM7IO

SBO2

I/O port 1

8-bit CMOS I/O port.

Each bit can be set individually as either an

input or output by the P1DIR register.

A pull-up resistor for each bit can be selected

individually by the P1PLU register.

At reset, the input mode (P10 to P17) is

selected, and pull-up resistor is disable.

P20

P21

P22

P23

P24

P25

P26

P27

I/O

SBT2

SBI2

SBO1

SBT1

SBI1

SBO0

SBT0

SBI0

I/O port 2

8-bit CMOS I/O port.

Each bit can be set individually as either an

input or output by the P2DIR register.

A pull-up resistor for each bit can be selected

individually by the P2PLU register.

At reset, the input mode (P20 to P27) is

selected, and pull-up resistor is disable.

P30

P31

P32

P33

P34

P35

P36

P37

I/O

TM0IO

TM1IO

TM2IO

TM3IO

TM4IO

TM5IO

TM8AIO

TM8BIO

I/O port 3

8-bit CMOS I/O port.

Each bit can be set individually as either an

input or output by the P3DIR register.

A pull-up resistor for ech bit can be selected

individually by the P3PLU register.

At reset, the input mode (P30 to P37) is

selected, pull-up resistor is disable.

TM1IO 数据表(PDF) 11 Page - Panasonic Semiconductor

TM1IO 数据表(HTML) 11 Page - Panasonic Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

数据表下载

链接网址

TM1IO 数据表(PDF) 11 Page - Panasonic Semiconductor

TM1IO 数据表(HTML) 11 Page - Panasonic Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

数据表 下载

链接网址

数据表下载