ATtiny15L datasheet(6/11 Pages) ATMEL

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ATtiny15L

1187DS–12/01

ATtiny15L Instruction Set Summary

Mnemonic

Operands

Description

Operation

Flags

# Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

Rd, Rr

Add Two Registers

← Rd + Rr

Z,C,N,V,H

ADC

Rd, Rr

Add with Carry Two Registers

← Rd + Rr + C

Z,C,N,V,H

SUB

Rd, Rr

Subtract Two Registers

← Rd - Rr

Z,C,N,V,H

SUBI

Rd, K

Subtract Constant from Register

← Rd - K

Z,C,N,V,H

SBC

Rd, Rr

Subtract with Carry Two Registers

← Rd - Rr - C

Z,C,N,V,H

SBCI

Rd, K

Subtract with Carry Constant from Reg.

← Rd - K - C

Z,C,N,V,H

AND

Rd, Rr

Logical AND Registers

← Rd • Rr

Z,N,V

ANDI

Rd, K

Logical AND Register and Constant

← Rd • K

Z,N,V

Rd, Rr

Logical OR Registers

← Rd v Rr

Z,N,V

ORI

Rd, K

Logical OR Register and Constant

← Rd v K

Z,N,V

EOR

Rd, Rr

Exclusive OR Registers

← Rd⊕Rr

Z,N,V

COM

One’s Complement

← $FF - Rd

Z,C,N,V

NEG

Two’s Complement

← $00 - Rd

Z,C,N,V,H

SBR

Rd, K

Set Bit(s) in Register

← Rd v K

Z,N,V

CBR

Rd, K

Clear Bit(s) in Register

← Rd • (FFh - K)

Z,N,V

INC

Increment

← Rd + 1

Z,N,V

DEC

Decrement

← Rd - 1

Z,N,V

TST

Test for Zero or Minus

← Rd • Rd

Z,N,V

CLR

Clear Register

← Rd⊕Rd

Z,N,V

SER

Set Register

← $FF

None

BRANCH INSTRUCTIONS

RJMP

Relative Jump

← PC + k + 1

None

RCALL

Relative Subroutine Call

← PC + k + 1

None

RET

Subroutine Return

← STACK

None

RETI

Interrupt Return

← STACK

CPSE

Rd, Rr

Compare, Skip if Equal

if (Rd = Rr) PC

← PC + 2 or 3

None

1/2

Rd, Rr

Compare

Rd - Rr

Z,N,V,C,H

CPC

Rd, Rr

Compare with Carry

Rd - Rr - C

Z,N,V,C,H

CPI

Rd, K

Compare Register with Immediate

Rd - K

Z,N,V,C,H

SBRC

Rr, b

Skip if Bit in Register Cleared

if (Rr(b) = 0) PC

← PC + 2 or 3

None

1/2

SBRS

Rr, b

Skip if Bit in Register is Set

if (Rr(b) = 1) PC

← PC + 2 or 3

None

1/2

SBIC

P, b

Skip if Bit in I/O Register Cleared

if (P(b) = 0) PC

← PC + 2 or 3

None

1/2

SBIS

P, b

Skip if Bit in I/O Register is Set

if (P(b) = 1) PC

← PC + 2 or 3

None

1/2

BRBS

s, k

Branch if Status Flag Set

if (SREG(s) = 1) then PC

← PC + k + 1

None

1/2

BRBC

s, k

Branch if Status Flag Cleared

if (SREG(s) = 0) then PC

← PC + k + 1

None

1/2

BREQ

Branch if Equal

if (Z = 1) then PC

← PC + k + 1

None

1/2

BRNE

Branch if Not Equal

if (Z = 0) then PC

← PC + k + 1

None

1/2

BRCS

Branch if Carry Set

if (C = 1) then PC

← PC + k + 1

None

1/2

BRCC

Branch if Carry Cleared

if (C = 0) then PC

← PC + k + 1

None

1/2

BRSH

Branch if Same or Higher

if (C = 0) then PC

← PC + k + 1

None

1/2

BRLO

Branch if Lower

if (C = 1) then PC

← PC + k + 1

None

1/2

BRMI

Branch if Minus

if (N = 1) then PC

← PC + k + 1

None

1/2

BRPL

Branch if Plus

if (N = 0) then PC

← PC + k + 1

None

1/2

BRGE

Branch if Greater or Equal, Signed

if (N

⊕ V= 0) then PC ← PC + k + 1

None

1/2

BRLT

Branch if Less Than Zero, Signed

if (N

⊕ V= 1) then PC ← PC + k + 1

None

1/2

BRHS

Branch if Half-carry Flag Set

if (H = 1) then PC

← PC + k + 1

None

1/2

BRHC

Branch if Half-carry Flag Cleared

if (H = 0) then PC

← PC + k + 1

None

1/2

BRTS

Branch if T-flag Set

if (T = 1) then PC

← PC + k + 1

None

1/2

BRTC

Branch if T-flag Cleared

if (T = 0) then PC

← PC + k + 1

None

1/2

BRVS

Branch if Overflow Flag is Set

if (V = 1) then PC

← PC + k + 1

None

1/2

BRVC

Branch if Overflow Flag is Cleared

if (V = 0) then PC

← PC + k + 1

None

1/2

BRIE

Branch if Interrupt Enabled

if (I = 1) then PC

← PC + k + 1

None

1/2

BRID

Branch if Interrupt Disabled

if (I = 0) then PC

← PC + k + 1

None

1/2

DATA TRANSFER INSTRUCTIONS

Rd, Z

Load Register Indirect

← (Z)

None

Z, Rr

Store Register Indirect

(Z)

← Rr

None

MOV

Rd, Rr

Move between Registers

← Rr

None

LDI

Rd, K

Load Immediate

← KNone

Rd, P

In Port

← PNone

OUT

P, Rr

Out Port

← Rr

None

LPM

Load Program Memory

← (Z)

None

BIT AND BIT-TEST INSTRUCTIONS

SBI

P, b

Set Bit in I/O Register

I/O(P,b)

← 1None

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