AX88196L datasheet(21/42 Pages) ASIX

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AX88196

Local CPU BUS MAC Controller

ASIX ELECTRONICS CORPORATION

4.9 Inter-frame gap (IFG) Offset 16H (Read/Write)

FIELD

NAME

DESCRIPTION

Reserved

6:0

IFG

Inter-frame Gap. Default value 15H.

4.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write)

FIELD

NAME

DESCRIPTION

Reserved

6:0

IFG

Inter-frame Gap Segment 1. Default value 0cH.

4.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write)

FIELD

NAME

DESCRIPTION

Reserved

6:0

IFG

Inter-frame Gap Segment 2. Default value 11H.

4.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write)

FIELD

NAME

DESCRIPTION

EECLK EECLK

EEPROM Clock

EEO

EEPROM Data Out

EEI

EEPROM Data In

EECS

EEPROM Chip Select

MDO

MII Data Out

MDI

MII Data In

MDIR

MII STA MDIO signal Direction

MII Read Control Bit, assert this bit let MDIO signal as the input signal. Deassert this bit

let MDIO as output signal.

MDC

MII Clock

4.13 Test Register (TR) Offset 15H (Write)

FIELD

NAME

DESCRIPTION

Reserved

MPSEL Media Priority Select : default value is logic 0

MPSEL

/SLINK

Media Selected

SNI

MII

Depand on MPSET bit

MPSET Media Set by Program : The signal is valid only when MPSEL is set to high.

When MPSET is logic 0 , SNI is selected.

When MPSET is logic 1 , MII is selected.

TF16T

Test for Collision, default value is logic 0

TPE

Test pin Enable, default value is logic 0

2:0

IFG

Select Test Pins Output, default value is logic 0

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