AS3630 datasheet(39/72 Pages) AMSCO

39 / 72 page

8A Supercap Flash Driver

AS3630 – 39

Figure AS3630 – 36:

ADC Timings

Once the conversion is finished ADC_convert returns to 00b,

status_adc_eoc is set, and the result data is available from

Note: The ADC input ranges and gains are described in Figure 6

subsection ADC.

I²C Mode Serial Data Bus

The AS3630 supports the I²C bus protocol. A device that sends

data onto the bus is defined as a transmitter and a device

receiving data as a receiver. The device that controls the

message is called a master. The devices that are controlled by

the master are referred to as slaves. A master device that

generates the serial clock (SCL), controls the bus access, and

generates the START and STOP conditions must control the bus.

The AS3630 operates as a slave on the I²C bus. Within the bus

specifications a standard mode (100kHz maximum clock rate)

and a fast mode (400kHz maximum clock rate) are defined. The

AS3630 works in both modes. Connections to the bus are made

through the open-drain I/O lines SDA and SCL.

The following bus protocol has been defined (Figure 37):

• Data transfer may be initiated only when the bus is not

busy.

• During data transfer, the data line must remain stable

whenever the clock line is HIGH. Changes in the data line

while the clock line is HIGH are interpreted as control

signals.

Accordingly, the following bus conditions have been defined:

Bus Not Busy

Both data and clock lines remain HIGH.

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AS3630 数据表(PDF) 39 Page - ams AG