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AS3608 数据表(PDF) 39 Page - ams AG

部件名 AS3608
功能描述  System PMU with HV Back Light Driver
PDF  68 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AMSCO [ams AG]
网页  http://www.ams.com
标志 AMSCO - ams AG

AS3608 数据表(HTML) 39 Page - ams AG

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www.austriamicrosystems.com
Revision 1.03
38 - 67
AS3608 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 21. CVDD3 Register
Name
Base
Default
CVDD3
2-wire serial
00h
Offset: 17h-3
CVDD3 DC/DC Buck Regulator Control Register
This is an extended register and needs to be enabled by writing 011b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
7
CVDD3_fast
0
R/W
Selects a faster regulation mode for CVDD3 suitable for larger load changes.
0: normal mode, Cext=10uF
1: fast mode, Cext=22uF required
6:0
VSEL_CVDD3<6:0>
000000
R/W
The voltage select bits set the DC/DC output voltage level and power the
DC/DC converter down.
00h: DC/DC powered down
01h-40h: CVDD1=0.6V+VSEL_CVDD1*12.5mV
41h-70h: CVDD1=1.4V+(VSEL_CVDD1-40h)*25mV
71h-7Fh: CVDD1=2.6V+(VSEL_CVDD1-70h)*50mV
Table 22. Hibernation Register
Name
Base
Default
Hibernation
2-wire serial
00h
Offset: 17h-4
PMU Hibernation Control Register
Hibernation starts when writing this register, except hibernation via GPIO is selected.
This is an extended register and needs to be enabled by writing 100b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input. This register MUST NOT be read back!!!
Bit
Bit Name
Default
Access
Bit Description
7-
0
n/a
6
KEEP_PVDD4
0
W
Keeps the programmed PVDD4 level during hibernation.
0: power down PVDD4
1: keep PVDD4
5
KEEP_PVDD3
0
W
Keeps the programmed PVDD3 level during hibernation.
0: power down PVDD3
1: keep PVDD3
4
KEEP_PVDD2
0
W
Keeps the programmed PVDD2 level during hibernation.
0: power down PVDD2
1: keep PVDD2
3
KEEP_PVDD1
0
W
Keeps the programmed PVDD1 level during hibernation.
0: power down PVDD1
1: keep PVDD1
2
KEEP_CVDD3
0
W
Keeps the programmed CVDD3 level during hibernation.
0: power down CVDD3
1: keep CVDD3
1
KEEP_CVDD2
0
W
Keeps the programmed CVDD2 level during hibernation.
0: power down CVDD2
1: keep CVDD2
0
KEEP_CVDD1
0
W
Keeps the programmed CVDD1 level during hibernation.
0: power down CVDD1
1: keep CVDD1



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