ams Datasheet

Page 11

[v1-00] 2015-Apr-01

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HLS-440P − Electrical Interface

Byte 7 Safety Byte CRC

Figure 15:

Byte 7 Safety Byte Order

The CRC byte shows the 7-bit CRC over byte 0-6 with the

Polynomial 0xE5.

PWM

This section describes the PWM output that is available in some

variants of HLS-440P.

Physical Interface

The electrical connector is the same as in the variants with CAN

bus interface (see Electrical Connector ). Type A has a

termination resistor while type B does not.

The PWM signal is created as a differential CAN signal on pin 3

and 4. A CAN signal is said to be in a dominant state when the

signal lines are separated (a dominant bit is transmitted). When

the signal lines are at the same voltage level, the state is

recessive. Recommended circuitry to convert CAN signals to

TTL is specified in a separate document, available on request.

The PWM signal is only an output signal. No other transmitting

devices should be attached to the bus.

The PWM Signal

The PWM signal has a period time of 255 μs. The rather short

period is chosen since modern CAN transceivers do not allow

for a longer dominant state.

The duration of the recessive state can be translated into output

(pulse width) ranges from 20 to 220 μs, which corresponds to 0

to 10% hydrogen. An error is shown as a 10 μs pulse width. At

startup the pulse width will be 255 μs (100% duty cycle) until

The figure below shows the output for 0% hydrogen (pulse

width of 20 μs).

Bit

MSB

7

6

5

4

3

2

1

LSB

0

Byte 7

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