V23839-R3x-L55

Pin Configuration

Preliminary Product Information

3

2004-06-25

Pin Description

Pin No.

Name

Logic Level

Function

1

V

N/A

Receiver Ground

2

V

N/A

Receiver Power

3

SD

LVTTL

Signal Detect

1) 5)

4

RD–

LVPECL

Inv. Received Data Out

2)

5

RD+

LVPECL

Received Data Out

2)

6

V

N/A

Transmitter Power

7

V

N/A

Transmitter Ground

8

TxDis

LVTTL

Transmitter Disable

3)

9

TD+

LVPECL

Transmit Data In

4)

10

TD–

LVPECL

Inv. Transmit Data In

4)

A

SDA

LVTTL

2-wire Data Interface

5)

B

SCL

LVTTL

2-wire Clock Interface

5)

C

Rate Select

6)

LVTTL

1 & 2 or 2 & 4 Gbit/s

7)

D

Tx Fault

LVTTL

Transmitter Fault

5)

MS

MS

N/A

Mounting Studs

8)

HL

HL

N/A

Housing Leads

9)

1)

Normal operation: Logic 1 output, represents that light is present at receiver input.

Fault condition: Logic 0 output.

2)

AC coupled inside transceiver. Must be terminated with 100

Ω differential at the user SERDES.

3)

A logic 0 switches the transmitter on. A logic 1 switches the transmitter off.

4)

AC coupled and 100

Ω differential termination inside the transceiver.

5)

Should be pulled up on host board to

V

6)

Not implemented.

7)

In accordance to SFF Committee SFF-8079 Draft.

8)

Mounting Studs are provided for transceiver mechanical attachment to the circuit board. They also provide an

optional connection of the transceiver to the equipment chassis ground.

9)

The transceiver Housing Leads are provided for additional signal grounding. The holes in the circuit board must

be included and be tied to signal ground (see EMI Recommendations).