TMP103

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SBOS545B – FEBRUARY 2011 – REVISED JANUARY 2016

6.6 Timing Requirements

See

(1)

FAST MODE

HIGH-SPEED MODE

UNIT

MIN

MAX

MIN

MAX

0.001

0.4

0.001

3.4

MHz

0.001

0.4

0.001

2.75

MHz

Bus free time between STOP and START condition

600

160

ns

Hold time after repeated START condition.

100

100

ns

After this period, the first clock is generated.

Repeated START condition setup time

100

100

ns

STOP condition setup Time

100

100

ns

Data hold time

20

400

10

125

ns

Data setup time

100

10

ns

1300

160

ns

1300

200

ns

SCL clock high period

600

60

ns

Clock/data fall time

300

ns

Clock/data rise time

300

160

ns

Clock/data rise time for SCLK

≤ 100 kHz

1000

ns

(1)

Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not guaranteed and not

production tested.

The TMP103 is two-wire and SMBus compatible. Figure 1 to Figure 5 describe the various operations on the

TMP103. Parameters for Figure 1 are defined in Timing Requirements. Bus definitions are:

Bus Idle: Both SDA and SCL lines remain high.

Start Data Transfer: A change in the state of the SDA line, from high to low, while the SCL line is high, defines

a START condition. Each data transfer is initiated with a START condition.

Stop Data Transfer: A change in the state of the SDA line from low to high while the SCL line is high defines a

STOP condition. Each data transfer is terminated with a repeated START or STOP condition.

Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and

is determined by the master device.

Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device

that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA

line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into

account. On a master receive, the termination of the data transfer can be signaled by the master generating a

Not-Acknowledge (1) on the last byte transmitted by the slave.

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