Startup

Startof

Conversion

Delay

(1)

26ms

26ms

TMP103

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SBOS545B – FEBRUARY 2011 – REVISED JANUARY 2016

After power up or general-call reset, the TMP103 immediately starts a conversion, as shown in Figure 13. The

first result is available after 26 ms (typical). The active quiescent current during conversion is 40

μA (typical at

(1)

Delay is set by CR1 and CR0.

Figure 13. Conversion Start

7.5.3 Shutdown Mode (M1 = 0, M0 = 0)

Shutdown mode saves maximum power by shutting down all device circuitry other than the serial interface,

reducing current consumption to typically less than 0.5

μA. Shutdown mode is enabled when bits M1 and M0 (in

the Configuration Register) = 00. The device shuts down when the current conversion is completed.

7.5.4 One-Shot (M1 = 0, M0 = 1)

The TMP103 features a One-Shot Temperature Measurement mode. When the device is in Shutdown mode,

writing a 01 to bits M1 and M0 starts a single temperature conversion. During the conversion, bits M1 and M0

read 01. The device returns to the shutdown state at the completion of the single conversion. After the

conversion, bits M1 and M0 read 00. This feature is useful for reducing power consumption in the TMP103 when

continuous temperature monitoring is not required.

As a result of the short conversion time, the TMP103 can achieve a higher conversion rate. A single conversion

typically takes 26 ms and a read can take place in less than 20

μs. When using One-Shot mode, 30 or more

conversions per second are possible.

7.5.5 Continuous Conversion Mode (M1 = 1)

When the TMP103 is in Continuous Conversion mode (M1 = 1), a single conversion is performed at a rate

determined by the conversion rate bits, CR1 and CR0 (in the Configuration Register). The TMP103 performs a

single conversion and then powers down and waits for the appropriate delay set by CR1 and CR0. See Table 1

for CR1 and CR0 settings.

7.5.6 Bus Overview

The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The

bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and

generates the START and STOP conditions.

To address a specific device, a START condition is initiated, indicated by pulling the data line (SDA) from a high

to low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the rising edge of the

clock, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the

slave being addressed responds to the master by generating an Acknowledge and pulling SDA low.

Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge Bit. During data

transfer, SDA must remain stable while SCL is high, because any change in SDA while SCL is high is interpreted

as a START or STOP signal.

Once all data have been transferred, the master generates a STOP condition indicated by pulling SDA from low

to high, while SCL is high.

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