ADP5300

Data Sheet

Rev. 0 | Page 18 of 21

INPUT CAPACITOR

An input capacitor is required to reduce the input voltage

ripple, input ripple current, and source impedance. Place the

input capacitor as close as possible to the PVIN pin. A low ESR

X7R or X5R capacitor is highly recommended to minimize the

input voltage ripple. Use the following equation to determine

the rms input current:



IN

OUT

IN

OUT

MAX

LOAD

RMS

V

V

V

V

I

I





)

(

For most applications, a 10 μF capacitor is sufficient. The input

capacitor can be increased without any limit for improved input

voltage filtering.

EFFICIENCY

Efficiency is the ratio of output power to input power. The high

efficiency of the ADP5300 has two distinct advantages. First,

only a small amount of power is lost in the dc-to-dc converter

package, which in turn reduces thermal constraints. Second, the

high efficiency delivers the maximum output power for the

given input power, thereby extending battery life in portable

applications.

Power Switch Conduction Losses

Power switch dc conduction losses are caused by the flow of

output current through the high-side, P-channel power switch

and the low-side, N-channel synchronous rectifier, which have

of power loss is approximated by

where:

IN

OUT

V

V

D 

The internal resistance of the power switches increases with

temperature and with the input voltage decrease.

Inductor Losses

Inductor conduction losses are caused by the flow of current

through the inductor, which has an internal DCR associated

with it. Larger size inductors have smaller DCR, which can

decrease inductor conduction losses. Inductor core losses relate

to the magnetic permeability of the core material. Because the

ADP5300 is a high switching frequency dc-to-dc regulator,

shielded ferrite core material is recommended because of its low

core losses and low electromagnetic interference (EMI).

To estimate the total amount of power lost in the inductor, use

the following equation:

Driver Losses

Driver losses are associated with the current drawn by the driver to

turn on and turn off the power devices at the switching frequency.

Each time a power device gate is turned on and turned off, the

driver transfers a charge from the input supply to the gate, and

then from the gate to ground.

Estimate driver losses using the following equation:

where:

is the gate capacitance of the internal high-side switch.

is the gate capacitance of the internal low-side switch.

is the switching frequency in PWM mode.

Transition Losses

Transition losses occur because the P-channel switch cannot

turn on or turn off instantaneously. In the middle of a switch

node transition, the power switch provides all of the inductor

current. The source to drain voltage of the power switch is half

of the input voltage, resulting in power loss. Transition losses

increase with both load current and input voltage and occur

twice for each switching cycle.

Use the following equation to estimate transition losses:

where:

is the rise time of the SW node.

is the fall time of the SW node.

CIRCUIT BOARD LAYOUT RECOMMENDATIONS

10µF

10V/XR5

0603

10µF

6.3V/XR5

0603

ADP5300

TOP VIEW

5.7

4.6

Figure 42. Typical PCB Layout