 2015 Microchip Technology Inc.

DS00001888A-page 21

MM7150

FIGURE 8-2:

POWER-ON RESET TIMING CHARACTERISTICS

FIGURE 8-3:

EXTERNAL RESET TIMING CHARACTERISTICS

Note 1:

The power-up period will be extended if the power-up sequence completes before the device exits from

2:

Includes interval voltage regulator stabilization delay.

Internal Voltage Regulator Enabled

SY00

Power-up Sequence

(Note 2)

Internal Voltage Regulator Enabled

CPU Starts Fetching Code

(Note 1)

Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)

SY02

MCLR#

(SY20)

BOR

(SY30)

Reset Sequence

CPU Starts Fetching Code

Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)

SY02

SY02