CAP1133 datasheet(9/63 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001625B-page 9

CAP1133

Note 3-4

The ALERT pin will not glitch high or low at power up if connected to VDD or another voltage.

Note 3-5

The SMCLK and SMDATA pins will not glitch low at power up if connected to VDD or another voltage.

Input Low Voltage

VIL

0.8

Leakage Current

ILEAK

±5

powered or unpowered

TA < 85°C

pull-up voltage < 3.6V if unpowered

SMBus Timing

Input Capacitance

CIN

5pF

Clock Frequency

fSMB

400

kHz

Spike Suppression

tSP

Bus Free Time Stop to

Start

tBUF

1.3

Start Setup Time

tSU:STA

0.6

Start Hold Time

tHD:STA

0.6

Stop Setup Time

tSU:STO

0.6

Data Hold Time

tHD:DAT

When transmitting to the master

Data Hold Time

tHD:DAT

0.3

When receiving from the master

Data Setup Time

tSU:DAT

0.6

Clock Low Period

tLOW

1.3

Clock High Period

tHIGH

0.6

Clock / Data Fall Time

tFALL

300

Min = 20+0.1CLOAD ns

Clock / Data Rise

Time

tRISE

300

Min = 20+0.1CLOAD ns

Capacitive Load

CLOAD

400

per bus line

TABLE 3-2:

ELECTRICAL SPECIFICATIONS (CONTINUED)

VDD = 3V to 3.6V, TA = 0°C to 85°C, all typical values at TA = 27°C unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

Conditions

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