USB3803 datasheet(13/99 Pages) MICROCHIP

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DS00001691B-page 13

USB3803

3.3.2

I/O TYPE DESCRIPTIONS

3.3.3

REFERENCE CLOCK

The REFCLK input is can be driven with a square wave from 0 V to VDD33_BYP. The USB3803 only uses the positive

edge of the clock. The duty cycle is not critical.

The USB3803 is tolerant to jitter on the reference clock. The REFCLK jitter should be limited to a peak to peak jitter of

less than 1 nS over a 10

μS time interval. If this level of jitter is exceeded the USB3803 high speed eye diagram may

be degraded.

To select the REFCLK input frequency, the REF_SEL pins must be set according to Table 3-3.

3.3V VDD Power

VDD33_BYP

Power

3.3V Regulator. A 4.7

μF (<1

Ω ESR) capacitor to

ground is required for regulator stability. The capaci-

tor should be placed as close as possible to the

USB3803.

Core Power Supply Input

VDD_CORE_REG

Power

Power supply to 1.2V regulator.

This power pin should be connected to VDD33_BYP

for single supply applications.

Refer to Section 9.0, Integrated Power Regulators for

power supply configuration options.

Battery Power Supply Input

VBAT

Power

Battery power supply.

Refer to Section 9.0 for power supply configuration

options.

VSS

Ground

TABLE 3-2:

USB3803 I/O TYPE DESCRIPTIONS

I/O Type

Description

Digital Input

Digital Output. Open Drain.

I/O

Digital Input or Output.

A-I/O

Analog Input or Output.

Power

DC input or Output.

Ground

Ground.

TABLE 3-3:

USB3803 REFERENCE CLOCK FREQUENCIES

REF_SEL[1:0]

Frequency (MHz)

‘00’

38.4

‘01’

26.0

‘10’

19.2

‘11’

12.0

TABLE 3-1:

PIN DESCRIPTIONS (CONTINUED)

Name

Symbol

Type

Description

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