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USB5534B 数据表(PDF) 63 Page - Microchip Technology |
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USB5534B 数据表(HTML) 63 Page - Microchip Technology |
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63 / 73 page  2012 - 2015 Microchip Technology Inc. DS00001681C-page 63 USB5534B 7.4 SMBus Timing The SMBus slave interface complies with the SMBus Specification Revision 1.0. See Section 2.1, AC Specifications on page 3 for more information. FIGURE 7-4: SMBUS SLAVE TIMING DIAGRAM TABLE 7-3: SMBUS SLAVE TIMING MODES Symbol ParameterMIN MAX Unit fSCL SM_CLK clock frequency 0 100 KHz tHD;STA Hold time START condition 4 - s tLOW LOW period of the SM_CLK clock 4.7 - s tHIGH HIGH period of the SM_CLK clock 4 - s tSU;STA Set-up time for a repeated START condition 4.7 - s tHD;DAT DATA hold time\ 0 - ns tSU;DAT DATA set-up time 250 - ns tR Rise time of both SM_DATA and SM_CLK signals - 1000 ns tF Fall time of both SM_CLK and SM_DATA lines - 300 ns tSU;STO Set-up time for a STOP condition 4 - s tBUF Bus free time between a STOP and START condition 4.7 - s SM_DATA SM_CLK tBUF tHD;STA tSU;STO tSU;STA tSU;DAT tHIGH tHD;DAT tHD;STA tLOW tR tF |
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