DS00001726B-page 19

USB2422

4.3.2.2

Block Read

A block read differs from a block write in that the repeated start condition exists to satisfy the SMBus specification’s

requirement for a change in the transfer direction.

4.3.2.3

Invalid Protocol Response Behavior

Note that any attempt to update registers with an invalid protocol will not be updated. The only valid protocols are write

block and read block (described above), where the hub only responds to the 7-bit hardware selected slave address

(0101100b).

4.3.3

SLAVE DEVICE TIMEOUT

Devices in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds

of the interrupted data byte. Slave devices must reset their communication and be able to receive a new START condi-

4.3.4

STRETCHING THE SCLK SIGNAL

The hub supports stretching of the SCLK by other devices on the SMBus. However, the hub does not stretch the SCLK.

4.3.5

SMBUS TIMING

The SMBus slave interface complies with the SMBus Specification Revision 1.0 2.. See Section 2.1, AC Specifications

on page 3 for more information.

4.3.6

BUS RESET SEQUENCE

The SMBus slave interface resets and returns to the idle state upon a START condition followed immediately by a STOP

condition.

4.3.7

SMBUS ALERT RESPONSE ADDRESS

The SMBALERT# signal is not supported by the hub.

FIGURE 4-3:

BLOCK READ

Note:

Some simple devices do not contain a clock low drive circuit; this simple kind of device typically resets its

communications port after a start or stop condition. The slave device timeout must be implemented.

1

S

S

Slave Address

Register Address

Wr

17

1

1

8

A

1

Slave Address

Rd

A

71

1

...

A

81

1

1

88

1

81

P

A

A

A

A

Byte Count = N

Data byte 2

Data byte 1

Data byte N