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RPC564L60L5BOSY 数据表(PDF) 119 Page - STMicroelectronics |
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RPC564L60L5BOSY 数据表(HTML) 119 Page - STMicroelectronics |
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119 / 137 page  DocID026934 Rev 1 119/137 RPC56EL60L5 Electrical characteristics 136 x 3.20.2 WKUP/NMI timing 3.20.3 IEEE 1149.1 JTAG interface timing Table 33. RESET electrical characteristics No . Symbol Parameter Conditions(1) Min Typ Max Unit 1Ttr D Output transition time output pin(2) CL = 25pF — — 12 ns CL = 50pF — — 25 CL = 100pF — — 40 2WFRST P nRESET input filtered pulse — — — 40 ns 3 WNFRS T P nRESET input not filtered pulse — 500 — — ns 1. VDD = 3.3 V ± 10%, TJ = –40 to +150 °C, unless otherwise specified 2. CL includes device and package capacitance (CPKG < 5 pF). Table 34. WKUP/NMI glitch filter No. Symbol Parameter Min Typ Max Unit 1WFNMI D NMI pulse width that is rejected — — 45 ns 2WNFNMI D NMI pulse width that is passed 205 — — ns Table 35. JTAG pin AC electrical characteristics No . Symbol Parameter Conditions Min Max Unit 1tJCYC D TCK cycle time — 62.5 — ns 2tJDC D TCK clock pulse width (measured at VDDE/2) — 40 60 % 3tTCKRISE D TCK rise and fall times (40%–70%) — — 3 ns 4 tTMSS, tTDIS D TMS, TDI data setup time — 5 — ns 5 tTMSH, tTDIH D TMS, TDI data hold time — 25 — ns 6tTDOV D TCK low to TDO data valid — — 20 ns 7tTDOI D TCK low to TDO data invalid — 0 — ns 8tTDOHZ D TCK low to TDO high impedance — — 20 ns 11 tBSDV D TCK falling edge to output valid — — 50 ns 12 tBSDVZ D TCK falling edge to output valid out of high impedance — — 50 ns 13 tBSDHZ D TCK falling edge to output high impedance — — 50 ns 14 tBSDST D Boundary scan input valid to TCK rising edge — 50 — ns 15 tBSDHT D TCK rising edge to boundary scan input invalid — 50 — ns |
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