A6986 datasheet(49/67 Pages) STMICROELECTRONICS

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A6986

Application notes

The master driving capability must be able to provide the proper signal levels at the SYNCH

pin (see Table 5 on page 8 - Synchronization section):

 Low level < VSYN THL= 0.7 V sinking 5 mA

 High level > VSYN THH = 1.2 V sourcing 0.7 mA

Figure 37. Master driving capability to synchronize the A6986

As anticipated above, in SLAVE mode the internal oscillator operates at 250 kHz typ. but the

slope compensation is dimensioned accordingly with FSW resistors so, even if the A6986

supports synchronization over the 275 kHz - 1.4 MHz frequency range, it is important to limit

the switching operation around a working point close to the selected frequency (FSW

resistor).

As a consequence, to guarantee the full output current capability and to prevent the

subharmonic oscillations the master must limit the driving frequency range within ± 20% of

the selected frequency.

A wider frequency range may generate subharmonic oscillation for duty > 50% or limit the

peak current capability (see IPK parameter in Table 5) since the internal slope compensation

signal may be saturated.

In order to guarantee the synchronization as a slave over distribution, temperature and the

output load, the external clock frequency must be lower than 1.4 MHz.

7.5.1

Input capacitor selection

The input capacitor voltage rating must be higher than the maximum input operating voltage

of the application. During the switching activity a pulsed current flows into the input capacitor

and so its RMS current capability must be selected accordingly with the application

conditions. Internal losses of the input filter depends on the ESR value so usually low ESR

capacitors (like multilayer ceramic capacitors) have higher RMS current capability. On the

other hand, given the RMS current value, lower ESR input filter has lower losses and so

contributes to higher conversion efficiency.

VSYN_TH_H

VSYN_TH_L

VCCM

5 mA

0.7 mA

A6986 数据表(PDF) 49 Page - STMicroelectronics

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