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L9959 数据表(PDF) 21 Page - STMicroelectronics

部件名 L9959
功能描述  Single and dual PMOS high-side H-bridge
PDF  49 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

L9959 数据表(HTML) 21 Page - STMicroelectronics

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L9959
Electrical specifications
48
3.8
SPI / logic electrical characteristics
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4.5 V ≤ VS ≤ 18 V, 4.5 V ≤ VCC ≤ 5.5 V; all outputs open; Tj = -40 °C to
150 °C, unless otherwise specified.
Table 21. Inputs: SI, SS, SCK, DIR, DIS and PWM; Output: SO
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
Inputs: SI, SS, SCK DIR, PWM
VIL
Input voltage low-level
VDD = 5 V
-0.3
-
0.75
V
VIH
Input voltage high-level
VDD = 5 V
1.75
-
VDD+0.3
V
VIHYS
Input hysteresis
VDD = 5 V
0.2
-
1.0
V
RPUin
Input pull-up resistor
VDD = 5 V
50
-
250
kΩ
IINx
PWM, DIR input current
VINx > 3.0V
-5
-
5
μA
CSIin(1)
SI input capacitance
-
-
-
10
pF
CSCKin(1) SCK input capacitance
-
-
-
10
pF
CSSin(1)
SS Input Capacitance
-
-
-
15
pF
CDIR,PWMin
(1)
DIR, PWM input capacitance
-
-
-
20
pF
Input: DIS
RDISPU
Pull-up resistor
0 V < VDIS < 2.1 V
10
-
45
kΩ
IDISx
DIS input current
VDIS > 3 V
-5
-
5
μA
CDIS in(1) DIS input capacitance
-
-
-
20
pF
tDIS
DIS pulse width
-
0.5
1
1.5
μs
Input pin disturbance (SI, SS, SCK DIR, PWM,DIS)
ΔVx_HL
Change of VIH and VIL during
inverse current on VS
Not subjected to test in
production.
-0.1
-
0.1
V
ΔISx
Change of input current of SPI
input pins during inverse
current on VS
-100
-
100
μA
Output: SO
VSOL
Output voltage low level
IOL = 2 mA,
0
-
0.4
V
VSOH
Output voltage high level
IOH = -2 mA
VDD-0.5
-
VDD
V
SRSO(1)
Slew rate
CLOAD = 200 pF
0.3
-
0.6
V/ns
ISOLK
Tristate leakage current
VSS = VDD
-10
-
10
μA
CSO out(1) SO output capacitance
-
-
-
10
pF
Output pin disturbance (SO)
ISOLK
Change of ISOLK during
inverse Current on VS
-
-100
-
100
μA
1. Not measured in production test. Parameter guaranteed by design.



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