LED1642GWXTTR datasheet(21/42 Pages) STMICROELECTRONICS

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LED1642GW

Configuration register

Figure 10. Channel current vs. gain register value

8.2

Error detection mode (CFG-7)

Stopping the normal activity of the display and turning on all driver channels allows the error

detection to be performed and failed LED or display defects to be checked.

The error detection is active when the CFG -7 bit of the configuration register is "0". The

diagnostics is performed as shown in Figure 11:

•

The LED has to be selected turning on the relative channel on the switch register

(powering on or off the output channels); the brightness register value for this channel

cannot be zero.

•

The normal error detection has to be selected in the configuration register (CFG-7=

"0"). The appropriate digital key to choose the type of detection (open, short or

combined) must be sent (see Table 7).

•

After the error detection starts, the channel under testing has to be turned on at least 1

μs (the LED is at the nominal current). Please note that, the output power-on depends

on PWCLK signal and in several applications this signal is not synchronized with the

serial interface clock (CLK pin). Therefore, to be sure that, between the detection start

and the detection end, the output power-on is 1

μs and moreover, that last power-on, in

the interval, starts at least 0.5

μs before the detection end pattern (see Figure 12), it is

suggested that the error detection should be performed just after the device startup

(brightness counter reset) with all channels ON, before applying PWCLK signal.

•

The result of the detection ("0" indicates a fault condition) is shifted out SDO, in 16

clock pulses after the "detection end command" is provided, first output bit represents

channel 15 (error data can be read in a way similar to configuration register data

reading as shown on Figure 13, 14, 15 and 16).

Please note that (with SDO delay off) output 15 detection result will be available just after

1st clock pulse rising edge, so it can be sampled on the rising edge of second clock pulse. In

the same way output 0 detection result will be available just after 16th clock pulse rising

edge, so it can be sampled on the rising edge of 17th CLK pulse.

AM13695V1

0.0

5.0

10.0

15.0

20.0

25.0

30.0

35.0

40.0

11 K R=0

11 K R=1

18 K R=0

IOUT

OUT

vs. gain

(R = range selection, REXT = 11 K or 18 K)

Gain register decimal value

18 K R=1

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