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LED2472GQTR 数据表(PDF) 23 Page - STMicroelectronics |
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LED2472GQTR 数据表(HTML) 23 Page - STMicroelectronics |
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23 / 39 page ![]() DocID024620 Rev 3 23/39 LED2472G Digital blocks Figure 12 shows an example of the effect of the output gradual delay on the RED color group outputs. Figure 12. Gradual delay on first four channels of RED color group 8.8 Data flow management (CFG 9-CFG 11) The 8x3 shift registers have a default RGB sequence serial data flow according to the table shown into the configuration register (bit CFG-9, CFG-10 and CFG-11). Figure 13 shows how serial data are loaded in accordance with the data flow sequence selected through the configuration register. The default sequence is RGB (first bit will be R8, last bit B1 then: R8- R1, G8-G1, B8-B1). Table 10. Gradual output delay values Delay time (ns) from the falling edge of xOE R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 G7 B7 R8 G8 B8 CFG-8 = “0” 0 10 20 30 40 50 60 70 CFG-8 = “1” 0 000 0 0 0 0 |
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