LSM303AGR datasheet(30/68 Pages) STMICROELECTRONICS

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Functionality

LSM303AGR

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DocID027765 Rev 5

4.3

IC interface

The complete measurement chain is composed of a low-noise capacitive amplifier which

converts the capacitive unbalancing of the MEMS sensor into an analog voltage using an

analog-to-digital converter.

The acceleration and magnetic data may be accessed through an I2C/SPI interface thus

making the device particularly suitable for direct interfacing with a microcontroller.

The LSM303AGR features a data-ready signal which indicates when new sets of measured

acceleration and magnetic data are available, thus simplifying data synchronization in the

digital system that uses the device.

4.4

FIFO

The FIFO buffer applies only to the accelerometer. The LSM303AGR embeds a 32-level

FIFO for each of the three output channels, X, Y and Z. This allows consistent power saving

for the system, since the host processor does not need to continuously poll data from the

sensor, but it can wake up only when needed and burst the significant data out from the

FIFO.

In order to enable the FIFO buffer, the FIFO_EN bit in CTRL_REG5_A (24h) must be set to

‘1’.

This buffer can work according to the following different modes: Bypass mode, FIFO mode,

Stream mode and Stream-to-FIFO mode. Each mode is selected by the FM [1:0] bits in

FIFO_CTRL_REG_A (2Eh). Programmable FIFO watermark level, FIFO empty or FIFO

overrun events can be enabled to generate dedicated interrupts on the INT_1_XL pin

(configuration through CTRL_REG3_A (22h)).

In the FIFO_SRC_REG_A (2Fh) register the EMPTY bit is equal to ‘1’ when all FIFO

samples are ready and FIFO is empty.

In the FIFO_SRC_REG_A (2Fh) register the WTM bit goes to ‘1’ if new data is written in the

buffer and FIFO_SRC_REG_A (2Fh) (FSS [4:0]) is greater than or equal to

FIFO_CTRL_REG_A (2Eh) (FTH [4:0]). FIFO_SRC_REG_A (2Fh) (WTM) goes to ‘0’ if

reading an X, Y, Z data slot from FIFO and FIFO_SRC_REG_A (2Fh) (FSS [4:0]) is less

than or equal to FIFO_CTRL_REG_A (2Eh) (FTH [4:0]).

In the FIFO_SRC_REG_A (2Fh) register the OVRN_FIFO bit is equal to ‘1’ if the FIFO slot

is overwritten.

4.4.1

Bypass mode

In Bypass mode the FIFO is not operational and for this reason it remains empty. For each

channel only the first address is used. The remaining FIFO levels are empty.

Bypass mode must be used in order to reset the FIFO buffer when a different mode is

operating (i.e. FIFO mode).

4.4.2

FIFO mode

In FIFO mode, the buffer continues filling data from the X, Y and Z accelerometer channels

until it is full (a set of 32 samples stored). When the FIFO is full, it stops collecting data from

the input channels and the FIFO content remains unchanged.

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