M95040-DRMF4TP datasheet(11/41 Pages) STMICROELECTRONICS

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M95040-A125 M95040-A145

Operating features

3.3

Hold mode

The Hold (HOLD) signal is used to pause any serial communications with the device without

resetting the clocking sequence.

The Hold mode starts when the Hold (HOLD) signal is driven low and the Serial Clock (C) is

low (as shown in Figure 4). During the Hold mode, the Serial Data output (Q) is high

impedance, and the signals present on Serial Data input (D) and Serial Clock (C) are not

decoded. The Hold mode ends when the Hold (HOLD) signal is driven high and the Serial

Clock (C) is or becomes low.

Figure 4. Hold mode activation

Deselecting the device while it is in Hold mode resets the paused communication.

3.4

Protocol control and data protection

3.4.1

Protocol control

The Chip Select (S) input offers a built-in safety feature, as the S input is edge-sensitive as

well as level-sensitive: after power-up, the device is not selected until a falling edge has first

been detected on Chip Select (S). This ensures that Chip Select (S) must have been high

prior to going low, in order to start the first operation.

For Write commands (WRITE, WRSR, WRID, LID) to be accepted and executed:

•

the Write Enable Latch (WEL) bit must be set by a Write Enable (WREN) instruction

•

a falling edge and a low state on Chip Select (S) during the whole command must be

decoded

•

instruction, address and input data must be sent as multiple of eight bits

•

the command must include at least one data byte

•

Chip Select (S) must be driven high exactly after a data byte boundary

Write command can be discarded at any time by a rising edge on Chip Select (S) outside of

a byte boundary.

To execute Read commands (READ, RDSR, RDID, RDLS), the device must decode:

•

a falling edge and a low level on Chip Select (S) during the whole command

•

instruction and address as multiples of eight bits (byte)

From this step, data bits are shifted out until the rising edge on Chip Select (S).

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