ST2100 datasheet(13/39 Pages) STMICROELECTRONICS

13 / 39 page

DocID025777 Rev 1

13/39

ST2100

Architecture description

3.8

Application subsystem



Configurable hardware engine for multiple HomePlug PHY and real-time MAC layers

processing supporting:

–

HomePlug AV and 1.0 standards

–

HomePlug Green PHY standard



Integrated analog front-end:

–

Programmable gain amplifier: gain range -12 dB to 48 dB

–

ADC and DAC

–

2.5 V, 150 mA voltage regulator

–

Zero crossing (ZC) comparator



Cryptographic coprocessor channels (C3), DMA based programmable engine, with

support for:

–

Advanced encryption standard (AES) cipher (128-, 192-, 256-bit keys) in ECB,

CBC, CTR modes

–

Data encryption standard (DES) and triple DES cipher in ECB and CBC modes

–

SHA-1, HMAC-SHA-1, SHA-256, HMAC-SHA-256, MD5, HMAC-MD5 digests

algorithms



Configurable serial port (SPORT) interface for external DSP and audio codec (ADC

and DAC in I2S mode)



Transport stream (TS) interface



Pulse generator and capture (PGC) (IR) for remote controls



4-channel I2S [“Digital Audio Interface” (DAI)]



24 application specific GPIOs:

–

Up to 4 GPIOs supporting PWM

–

Up to 4 GPIOs supporting double PWM.

3.9

Clock and reset system



The system clocks are generated by:

–

Two fully programmable PLLs. One is used to generate a clock for CPU and

AMBA AHB bus and the other is used in case the DDR clock has to be different

(asynchronous) with respect to the CPU clock.

–

One “high precision” clock synthesizer with 4 outputs providing different

frequencies for the various IPs



Fully programmable control of the clock and reset signals for all the slave blocks

allowing sophisticated power management.

ST2100 数据表(PDF) 13 Page - STMicroelectronics

ST2100 数据表(HTML) 13 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

数据表下载