C164CL datasheet(30/79 Pages) INFINEON

30 / 79 page

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

Serial Channels

Serial communication with other microcontrollers, processors, terminals or external

peripheral components is provided by two serial interfaces with different functionality, an

Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous

Serial Channel (SSC).

The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller

families and supports full-duplex asynchronous communication at up to 781 Kbit/s and

half-duplex synchronous communication at up to 3.1 Mbit/s (@ 25 MHz CPU clock).

A dedicated baud rate generator allows to set up all standard baud rates without

oscillator tuning. For transmission, reception and error handling 4 separate interrupt

vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or

received, preceded by a start bit and terminated by one or two stop bits. For

multiprocessor communication, a mechanism to distinguish address from data bytes has

been included (8-bit data plus wake up bit mode).

In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a

shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop

back option is available for testing purposes.

A number of optional hardware error detection capabilities has been included to increase

the reliability of data transfers. A parity bit can automatically be generated on

transmission or be checked on reception. Framing error detection allows to recognize

data frames with missing stop bits. An overrun error will be generated, if the last

character received has not been read out of the receive buffer register at the time the

reception of a new character is complete.

The SSC supports full-duplex synchronous communication at up to 6.25 Mbit/s

(@ 25 MHz CPU clock). It may be configured so it interfaces with serially linked

peripheral components. A dedicated baud rate generator allows to set up all standard

baud rates without oscillator tuning. For transmission, reception and error handling

3 separate interrupt vectors are provided.

The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift

clock which can be generated by the SSC (master mode) or by an external master (slave

mode). The SSC can start shifting with the LSB or with the MSB and allows the selection

of shifting and latching clock edges as well as the clock polarity.

A number of optional hardware error detection capabilities has been included to increase

the reliability of data transfers. Transmit and receive error supervise the correct handling

of the data buffer. Phase and baudrate error detect incorrect serial data.

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