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L9662 数据表(PDF) 41 Page - STMicroelectronics |
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L9662 数据表(HTML) 41 Page - STMicroelectronics |
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41 / 80 page  DocID028325 Rev 1 41/80 L9662 Functional description 79 Bit [D9:D8] Bits used to set the firing current/time for all channels. The default state is ‘00’ (1.2A/2ms min.) Bits [D7:D0] The soft reset for the ASIC, which includes deployment driver/diagnostics and satellite functions, is achieved by writing 0xAA and 0x55 within two subsequent 16-bit SPI transmissions. If the sequence is broken, the processor will be required to re-transmit the sequence. The device will not reset if the sequence is not completed within two subsequent 16- bit SPI transmissions. When soft reset command is received, the device reset its deployment driver’s internal logic and timer, satellite internal logic including all internal registers. The effects of a soft reset is the same as a of POR event, except MISO response. Bit D0 used to report the soft reset sequence status. If valid soft reset MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MOSI Command for Configuration Mode 1 0 0 P R/W SWR 0 CL Set bits Software Reset Sequence bits MISO Response for Configuration Mode 1 (Except for Soft Reset/D11=1 and appropriate pattern) 0 0 P R/W SWR 0 CL Set bits 0 0 0 0 0 0 1 0 Table 17. Configuration mode 1 bit MOSI command MISO response State Description D15 0 Mode bits See above D14 0 See above D13 Odd Parity – Includes all 16 bits Odd Parity – Includes all 16 bits D12 0 Read (default) - When D12=’0’ bits D11 to D0 are ignored R/W bit 1 Write – Allows Soft reset and deployment programming D11 0 Sets Deployment Condition for ALL channels - When D11=’0’ bits D7 to D0 are ignored See above 1 Soft Reset Sequence (deployment circuit only) – bits D8 and D9 are ignored D10 0 See above D9 - Sets Deployment Conditions 00 = 1.2A/2ms (Default) 01 = 1.5A/2ms 10 = 1.75A/0.65ms 11 = 1.75A/1ms Internal Stored Value CL bits D8 - D7 – D2 - Software Reset-sequence See above D1 - see above D0 - See above |
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